Merge tag 'usb-5.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/phy/amlogic,meson8b-usb2-phy.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Amlogic Meson8, Meson8b, Meson8m2 and GXBB USB2 PHY

maintainers:

  - Martin Blumenstingl <martin.blumenstingl@googlemail.com>

properties:

  compatible:

    oneOf:

      - items:

          - enum:

              - amlogic,meson8-usb2-phy

              - amlogic,meson8b-usb2-phy

              - amlogic,meson8m2-usb2-phy

          - const: amlogic,meson-mx-usb2-phy

      - const: amlogic,meson-gxbb-usb2-phy

  reg:

    maxItems: 1

  clocks:

    minItems: 2

  clock-names:

    items:

      - const: usb_general

      - const: usb

  resets:

    minItems: 1

  "#phy-cells":

    const: 0

  phy-supply:

    description:

      Phandle to a regulator that provides power to the PHY. This

      regulator will be managed during the PHY power on/off sequence.

required:

  - compatible

  - reg

  - clocks

  - clock-names

  - "#phy-cells"

additionalProperties: false

examples:

  - |

    usb-phy@c0000000 {

      compatible = "amlogic,meson-gxbb-usb2-phy";

      reg = <0xc0000000 0x20>;

      resets = <&reset_usb_phy>;

      clocks = <&clk_usb_general>, <&reset_usb>;

      clock-names = "usb_general", "usb";

      phy-supply = <&usb_vbus>;

      #phy-cells = <0>;

    };

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

# Copyright (c) 2020 NXP

%YAML 1.2

---

$id: "http://devicetree.org/schemas/phy/cdns,salvo-phy.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Cadence SALVO PHY

maintainers:

  - Peter Chen <peter.chen@nxp.com>

properties:

  compatible:

    enum:

      - nxp,salvo-phy

  reg:

    maxItems: 1

  clocks:

    maxItems: 1

  clock-names:

    items:

      - const: salvo_phy_clk

  power-domains:

    maxItems: 1

  "#phy-cells":

    const: 0

required:

  - compatible

  - reg

  - "#phy-cells"

additionalProperties: false

examples:

  - |

    #include <dt-bindings/firmware/imx/rsrc.h>

    usb3phy: usb3-phy@5b160000 {

        compatible = "nxp,salvo-phy";

        reg = <0x5b160000 0x40000>;

        clocks = <&usb3_lpcg 4>;

        clock-names = "salvo_phy_clk";

        power-domains = <&pd IMX_SC_R_USB_2_PHY>;

        #phy-cells = <0>;

    };

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel ComboPhy Subsystem

maintainers:

  - Dilip Kota <eswara.kota@linux.intel.com>

description: |

  Intel Combophy subsystem supports PHYs for PCIe, EMAC and SATA

  controllers. A single Combophy provides two PHY instances.

properties:

  $nodename:

    pattern: "combophy(@.*|-[0-9a-f])*$"

  compatible:

    items:

      - const: intel,combophy-lgm

      - const: intel,combo-phy

  clocks:

    maxItems: 1

  reg:

    items:

      - description: ComboPhy core registers

      - description: PCIe app core control registers

  reg-names:

    items:

      - const: core

      - const: app

  resets:

    maxItems: 4

  reset-names:

    items:

      - const: phy

      - const: core

      - const: iphy0

      - const: iphy1

  intel,syscfg:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    description: Chip configuration registers handle and ComboPhy instance id

  intel,hsio:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    description: HSIO registers handle and ComboPhy instance id on NOC

  intel,aggregation:

    type: boolean

    description: |

      Specify the flag to configure ComboPHY in dual lane mode.

  intel,phy-mode:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      Mode of the two phys in ComboPhy.

      See dt-bindings/phy/phy.h for values.

  "#phy-cells":

    const: 1

required:

  - compatible

  - clocks

  - reg

  - reg-names

  - intel,syscfg

  - intel,hsio

  - intel,phy-mode

  - "#phy-cells"

additionalProperties: false

examples:

  - |

    #include <dt-bindings/phy/phy.h>

    combophy@d0a00000 {

        compatible = "intel,combophy-lgm", "intel,combo-phy";

        clocks = <&cgu0 1>;

        #phy-cells = <1>;

        reg = <0xd0a00000 0x40000>,

              <0xd0a40000 0x1000>;

        reg-names = "core", "app";

        resets = <&rcu0 0x50 6>,

                 <&rcu0 0x50 17>,

                 <&rcu0 0x50 23>,

                 <&rcu0 0x50 24>;

        reset-names = "phy", "core", "iphy0", "iphy1";

        intel,syscfg = <&sysconf 0>;

        intel,hsio = <&hsiol 0>;

        intel,phy-mode = <PHY_TYPE_PCIE>;

        intel,aggregation;

    };

* Amlogic Meson GXL and GXM USB3 PHY and OTG detection binding

Required properties:

- compatible:	Should be "amlogic,meson-gxl-usb3-phy"

- #phys-cells:	must be 0 (see phy-bindings.txt in this directory)

- reg:		The base address and length of the registers

- interrupts:	the interrupt specifier for the OTG detection

- clocks:	phandles to the clocks for

		- the USB3 PHY

		- and peripheral mode/OTG detection

- clock-names:	must contain "phy" and "peripheral"

- resets:	phandle to the reset lines for:

		- the USB3 PHY and

		- peripheral mode/OTG detection

- reset-names:	must contain "phy" and "peripheral"

Optional properties:

- phy-supply:	see phy-bindings.txt in this directory

Example:

	usb3_phy0: phy@78080 {

		compatible = "amlogic,meson-gxl-usb3-phy";

		#phy-cells = <0>;

		reg = <0x0 0x78080 0x0 0x20>;

		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&clkc CLKID_USB_OTG>, <&clkc_AO CLKID_AO_CEC_32K>;

		clock-names = "phy", "peripheral";

		resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>;

		reset-names = "phy", "peripheral";

	};

* Amlogic Meson8, Meson8b and GXBB USB2 PHY

Required properties:

- compatible:	Depending on the platform this should be one of:

	"amlogic,meson8-usb2-phy"

	"amlogic,meson8b-usb2-phy"

	"amlogic,meson-gxbb-usb2-phy"

- reg:		The base address and length of the registers

- #phys-cells:	should be 0 (see phy-bindings.txt in this directory)

- clocks:	phandle and clock identifier for the phy clocks

- clock-names:	"usb_general" and "usb"

Optional properties:

- resets:	reference to the reset controller

- phy-supply:	see phy-bindings.txt in this directory

Example:

usb0_phy: usb-phy@c0000000 {

	compatible = "amlogic,meson-gxbb-usb2-phy";

	#phy-cells = <0>;

	reg = <0x0 0xc0000000 0x0 0x20>;

	resets = <&reset RESET_USB_OTG>;

	clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;

	clock-names = "usb_general", "usb";

	phy-supply = <&usb_vbus>;

};