Commit e5daa1dd authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2014-05-06' of git://anongit.freedesktop.org/drm-intel into drm-next 

- ring init improvements (Chris)
- vebox2 support (Zhao Yakui)
- more prep work for runtime pm on Baytrail (Imre)
- eDram support for BDW (Ben)
- prep work for userptr support (Chris)
- first parts of the encoder->mode_set callback removal (Daniel)
- 64b reloc fixes (Ben)
- first part of atomic plane updates (Ville)

* tag 'drm-intel-next-2014-05-06' of git://anongit.freedesktop.org/drm-intel: (75 commits)
  drm/i915: Remove useless checks from primary enable/disable
  drm/i915: Merge LP1+ watermarks in safer way
  drm/i915: Make sure computed watermarks never overflow the registers
  drm/i915: Add pipe update trace points
  drm/i915: Perform primary enable/disable atomically with sprite updates
  drm/i915: Make sprite updates atomic
  drm/i915: Support 64b relocations
  drm/i915: Support 64b execbuf
  drm/i915/sdvo: Remove ->mode_set callback
  drm/i915/crt: Remove ->mode_set callback
  drm/i915/tv: Remove ->mode_set callback
  drm/i915/tv: Rip out pipe-disabling nonsense from ->mode_set
  drm/i915/tv: De-magic device check
  drm/i915/tv: extract set_color_conversion
  drm/i915/tv: extract set_tv_mode_timings
  drm/i915/dvo: Remove ->mode_set callback
  drm/i915: Make encoder->mode_set callbacks optional
  drm/i915: Make primary_enabled match the actual hardware state
  drm/i915: Move ring_begin to signal()
  drm/i915: Virtualize the ringbuffer signal func
  ...
parents 425a9a3a 10efa932

Documentation/DocBook/drm.tmpl

+5 −0
Original line number Diff line number Diff line
@@ -2942,6 +2942,11 @@ int num_ioctls;</synopsis> 
	This sections covers all things related to the GEM implementation in the

	i915 driver.

      </para>

      <sect2>

        <title>Batchbuffer Parsing</title>

!Pdrivers/gpu/drm/i915/i915_cmd_parser.c batch buffer command parser

!Idrivers/gpu/drm/i915/i915_cmd_parser.c

      </sect2>

    </sect1>

  </chapter>

</part>

drivers/gpu/drm/i915/i915_cmd_parser.c

+2 −2
Original line number Diff line number Diff line
@@ -28,7 +28,7 @@ 
#include "i915_drv.h"



/**

 * DOC: i915 batch buffer command parser

 * DOC: batch buffer command parser

 *

 * Motivation:

 * Certain OpenGL features (e.g. transform feedback, performance monitoring)
@@ -919,7 +919,7 @@ int i915_parse_cmds(struct intel_ring_buffer *ring, 
			DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n",

					 *cmd,

					 length,

					 (unsigned long)(batch_end - cmd));

					 batch_end - cmd);

			ret = -EINVAL;

			break;

		}

drivers/gpu/drm/i915/i915_debugfs.c

+18 −48
Original line number Diff line number Diff line
@@ -1239,9 +1239,13 @@ static int vlv_drpc_info(struct seq_file *m) 
	u32 rpmodectl1, rcctl1;

	unsigned fw_rendercount = 0, fw_mediacount = 0;



	intel_runtime_pm_get(dev_priv);



	rpmodectl1 = I915_READ(GEN6_RP_CONTROL);

	rcctl1 = I915_READ(GEN6_RC_CONTROL);



	intel_runtime_pm_put(dev_priv);



	seq_printf(m, "Video Turbo Mode: %s\n",

		   yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));

	seq_printf(m, "Turbo enabled: %s\n",
@@ -1261,6 +1265,11 @@ static int vlv_drpc_info(struct seq_file *m) 
			(I915_READ(VLV_GTLC_PW_STATUS) &

				VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");



	seq_printf(m, "Render RC6 residency since boot: %u\n",

		   I915_READ(VLV_GT_RENDER_RC6));

	seq_printf(m, "Media RC6 residency since boot: %u\n",

		   I915_READ(VLV_GT_MEDIA_RC6));



	spin_lock_irq(&dev_priv->uncore.lock);

	fw_rendercount = dev_priv->uncore.fw_rendercount;

	fw_mediacount = dev_priv->uncore.fw_mediacount;
@@ -1689,6 +1698,9 @@ static int i915_context_status(struct seq_file *m, void *unused) 
	}



	list_for_each_entry(ctx, &dev_priv->context_list, link) {

		if (ctx->obj == NULL)

			continue;



		seq_puts(m, "HW context ");

		describe_ctx(m, ctx);

		for_each_ring(ring, dev_priv, i)
@@ -1898,53 +1910,6 @@ static int i915_ppgtt_info(struct seq_file *m, void *data) 
	return 0;

}



static int i915_dpio_info(struct seq_file *m, void *data)

{

	struct drm_info_node *node = (struct drm_info_node *) m->private;

	struct drm_device *dev = node->minor->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	int ret;





	if (!IS_VALLEYVIEW(dev)) {

		seq_puts(m, "unsupported\n");

		return 0;

	}



	ret = mutex_lock_interruptible(&dev_priv->dpio_lock);

	if (ret)

		return ret;



	seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));



	seq_printf(m, "DPIO PLL DW3 CH0 : 0x%08x\n",

		   vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(0)));

	seq_printf(m, "DPIO PLL DW3 CH1: 0x%08x\n",

		   vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(1)));



	seq_printf(m, "DPIO PLL DW5 CH0: 0x%08x\n",

		   vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(0)));

	seq_printf(m, "DPIO PLL DW5 CH1: 0x%08x\n",

		   vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(1)));



	seq_printf(m, "DPIO PLL DW7 CH0: 0x%08x\n",

		   vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(0)));

	seq_printf(m, "DPIO PLL DW7 CH1: 0x%08x\n",

		   vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(1)));



	seq_printf(m, "DPIO PLL DW10 CH0: 0x%08x\n",

		   vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(0)));

	seq_printf(m, "DPIO PLL DW10 CH1: 0x%08x\n",

		   vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(1)));



	seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",

		   vlv_dpio_read(dev_priv, PIPE_A, VLV_CMN_DW0));



	mutex_unlock(&dev_priv->dpio_lock);



	return 0;

}



static int i915_llc(struct seq_file *m, void *data)

{

	struct drm_info_node *node = (struct drm_info_node *) m->private;
@@ -3299,9 +3264,15 @@ static int 
i915_wedged_set(void *data, u64 val)

{

	struct drm_device *dev = data;

	struct drm_i915_private *dev_priv = dev->dev_private;



	intel_runtime_pm_get(dev_priv);



	i915_handle_error(dev, val,

			  "Manually setting wedged to %llu", val);



	intel_runtime_pm_put(dev_priv);



	return 0;

}
@@ -3803,7 +3774,6 @@ static const struct drm_info_list i915_debugfs_list[] = { 
	{"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},

	{"i915_swizzle_info", i915_swizzle_info, 0},

	{"i915_ppgtt_info", i915_ppgtt_info, 0},

	{"i915_dpio", i915_dpio_info, 0},

	{"i915_llc", i915_llc, 0},

	{"i915_edp_psr_status", i915_edp_psr_status, 0},

	{"i915_sink_crc_eDP1", i915_sink_crc, 0},

drivers/gpu/drm/i915/i915_dma.c

+6 −6
Original line number Diff line number Diff line
@@ -1340,7 +1340,7 @@ static int i915_load_modeset_init(struct drm_device *dev) 


	ret = i915_gem_init(dev);

	if (ret)

		goto cleanup_power;

		goto cleanup_irq;



	INIT_WORK(&dev_priv->console_resume_work, intel_console_resume);
@@ -1349,10 +1349,8 @@ static int i915_load_modeset_init(struct drm_device *dev) 
	/* Always safe in the mode setting case. */

	/* FIXME: do pre/post-mode set stuff in core KMS code */

	dev->vblank_disable_allowed = true;

	if (INTEL_INFO(dev)->num_pipes == 0) {

		intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);

	if (INTEL_INFO(dev)->num_pipes == 0)

		return 0;

	}



	ret = intel_fbdev_init(dev);

	if (ret)
@@ -1387,8 +1385,7 @@ cleanup_gem: 
	mutex_unlock(&dev->struct_mutex);

	WARN_ON(dev_priv->mm.aliasing_ppgtt);

	drm_mm_takedown(&dev_priv->gtt.base.mm);

cleanup_power:

	intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);

cleanup_irq:

	drm_irq_uninstall(dev);

cleanup_gem_stolen:

	i915_gem_cleanup_stolen(dev);
@@ -1573,6 +1570,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
	spin_lock_init(&dev_priv->backlight_lock);

	spin_lock_init(&dev_priv->uncore.lock);

	spin_lock_init(&dev_priv->mm.object_stat_lock);

	dev_priv->ring_index = 0;

	mutex_init(&dev_priv->dpio_lock);

	mutex_init(&dev_priv->modeset_restore_lock);
@@ -1930,6 +1928,8 @@ void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) 
{

	struct drm_i915_file_private *file_priv = file->driver_priv;



	if (file_priv && file_priv->bsd_ring)

		file_priv->bsd_ring = NULL;

	kfree(file_priv);

}

drivers/gpu/drm/i915/i915_drv.c

+86 −24
Original line number Diff line number Diff line
@@ -279,6 +279,26 @@ static const struct intel_device_info intel_broadwell_m_info = { 
	GEN_DEFAULT_PIPEOFFSETS,

};



static const struct intel_device_info intel_broadwell_gt3d_info = {

	.gen = 8, .num_pipes = 3,

	.need_gfx_hws = 1, .has_hotplug = 1,

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,

	.has_llc = 1,

	.has_ddi = 1,

	.has_fbc = 1,

	GEN_DEFAULT_PIPEOFFSETS,

};



static const struct intel_device_info intel_broadwell_gt3m_info = {

	.gen = 8, .is_mobile = 1, .num_pipes = 3,

	.need_gfx_hws = 1, .has_hotplug = 1,

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,

	.has_llc = 1,

	.has_ddi = 1,

	.has_fbc = 1,

	GEN_DEFAULT_PIPEOFFSETS,

};



/*

 * Make sure any device matches here are from most specific to most

 * general.  For example, since the Quanta match is based on the subsystem
@@ -311,8 +331,10 @@ static const struct intel_device_info intel_broadwell_m_info = { 
	INTEL_HSW_M_IDS(&intel_haswell_m_info), \

	INTEL_VLV_M_IDS(&intel_valleyview_m_info),	\

	INTEL_VLV_D_IDS(&intel_valleyview_d_info),	\

	INTEL_BDW_M_IDS(&intel_broadwell_m_info),	\

	INTEL_BDW_D_IDS(&intel_broadwell_d_info)

	INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),	\

	INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),	\

	INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),	\

	INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info)



static const struct pci_device_id pciidlist[] = {		/* aka */

	INTEL_PCI_IDS,
@@ -551,7 +573,6 @@ static int i915_drm_thaw_early(struct drm_device *dev) 
static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	int error = 0;



	if (drm_core_check_feature(dev, DRIVER_MODESET) &&

	    restore_gtt_mappings) {
@@ -569,8 +590,10 @@ static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings) 
		drm_mode_config_reset(dev);



		mutex_lock(&dev->struct_mutex);



		error = i915_gem_init_hw(dev);

		if (i915_gem_init_hw(dev)) {

			DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");

			atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);

		}

		mutex_unlock(&dev->struct_mutex);



		/* We need working interrupts for modeset enabling ... */
@@ -613,7 +636,7 @@ static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings) 
	mutex_unlock(&dev_priv->modeset_restore_lock);



	intel_runtime_pm_put(dev_priv);

	return error;

	return 0;

}



static int i915_drm_thaw(struct drm_device *dev)
@@ -758,11 +781,8 @@ int i915_reset(struct drm_device *dev) 
		 * reset and the re-install of drm irq. Skip for ironlake per

		 * previous concerns that it doesn't respond well to some forms

		 * of re-init after reset. */

		if (INTEL_INFO(dev)->gen > 5) {

			mutex_lock(&dev->struct_mutex);

			intel_enable_gt_powersave(dev);

			mutex_unlock(&dev->struct_mutex);

		}

		if (INTEL_INFO(dev)->gen > 5)

			intel_reset_gt_powersave(dev);



		intel_hpd_init(dev);

	} else {
@@ -896,13 +916,6 @@ static int i915_pm_poweroff(struct device *dev) 
	return i915_drm_freeze(drm_dev);

}



static void snb_runtime_suspend(struct drm_i915_private *dev_priv)

{

	struct drm_device *dev = dev_priv->dev;



	intel_runtime_pm_disable_interrupts(dev);

}



static void hsw_runtime_suspend(struct drm_i915_private *dev_priv)

{

	hsw_enable_pc8(dev_priv);
@@ -912,12 +925,7 @@ static void snb_runtime_resume(struct drm_i915_private *dev_priv) 
{

	struct drm_device *dev = dev_priv->dev;



	intel_runtime_pm_restore_interrupts(dev);

	intel_init_pch_refclk(dev);

	i915_gem_init_swizzling(dev);

	mutex_lock(&dev_priv->rps.hw_lock);

	gen6_update_ring_freq(dev);

	mutex_unlock(&dev_priv->rps.hw_lock);

}



static void hsw_runtime_resume(struct drm_i915_private *dev_priv)
@@ -925,19 +933,67 @@ static void hsw_runtime_resume(struct drm_i915_private *dev_priv) 
	hsw_disable_pc8(dev_priv);

}



int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)

{

	u32 val;

	int err;



	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);

	WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);



#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)

	/* Wait for a previous force-off to settle */

	if (force_on) {

		err = wait_for(!COND, 20);

		if (err) {

			DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",

				  I915_READ(VLV_GTLC_SURVIVABILITY_REG));

			return err;

		}

	}



	val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);

	val &= ~VLV_GFX_CLK_FORCE_ON_BIT;

	if (force_on)

		val |= VLV_GFX_CLK_FORCE_ON_BIT;

	I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);



	if (!force_on)

		return 0;



	err = wait_for(COND, 20);

	if (err)

		DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",

			  I915_READ(VLV_GTLC_SURVIVABILITY_REG));



	return err;

#undef COND

}



static int intel_runtime_suspend(struct device *device)

{

	struct pci_dev *pdev = to_pci_dev(device);

	struct drm_device *dev = pci_get_drvdata(pdev);

	struct drm_i915_private *dev_priv = dev->dev_private;



	if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))

		return -ENODEV;



	WARN_ON(!HAS_RUNTIME_PM(dev));

	assert_force_wake_inactive(dev_priv);



	DRM_DEBUG_KMS("Suspending device\n");



	/*

	 * rps.work can't be rearmed here, since we get here only after making

	 * sure the GPU is idle and the RPS freq is set to the minimum. See

	 * intel_mark_idle().

	 */

	cancel_work_sync(&dev_priv->rps.work);

	intel_runtime_pm_disable_interrupts(dev);



	if (IS_GEN6(dev))

		snb_runtime_suspend(dev_priv);

		;

	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))

		hsw_runtime_suspend(dev_priv);

	else
@@ -981,6 +1037,12 @@ static int intel_runtime_resume(struct device *device) 
	else

		WARN_ON(1);



	i915_gem_init_swizzling(dev);

	gen6_update_ring_freq(dev);



	intel_runtime_pm_restore_interrupts(dev);

	intel_reset_gt_powersave(dev);



	DRM_DEBUG_KMS("Device resumed\n");

	return 0;

}

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