Commit e5aeced6 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'spi-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi 

Pull spi updates from Mark Brown:
 "A few core tweaks this time together with the usual collection of
  driver specific updates and fixes plus a larger than average selection
  of new device support:

   - fix DMA mapping of unaligned vmalloc() buffers

   - statistics tracking transfer volumes exposed via sysfs

   - new drivers for Freescale MPC5125, Intel Sunrise Point, Mediatek
     SoCs, and Netlogic XLP SoCs"

* tag 'spi-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (66 commits)
  spi: sh-msiof: Fix FIFO size to 64 word from 256 word
  spi: fsl-(e)spi: Fix checking return value of devm_ioremap_resource
  spi: Add DT bindings documentation for Netlogic XLP SPI controller
  spi/xlp: SPI controller driver for Netlogic XLP SoCs
  spi: fsl-espi: add runtime PM
  spi: fsl-(e)spi: simplify cleanup code
  spi: fsl-(e)spi: migrate to using devm_ functions to simplify cleanup
  spi: mediatek: fix SPI_CMD_PAUSE_IE macro error
  spi: check bits_per_word in spi_setup
  spi: mediatek: replace *_time name
  spi: mediatek: add PM clk_prepare_enable fail flow
  spi: mediatek: replace int with u32, delete TAB and define MTK_SPI_PAUSE_INT_STATUS marco
  spi: mediatek: add linux/io.h include file
  spi/bcm63xx-hsspi: add support for dual spi read/write
  spi: dw: Allow interface drivers to limit data I/O to word sizes
  dt: snps,dw-apb-ssi: Document new I/O data register width property
  spi: Fall back to master maximum speed if no slave speed specified
  spi: mediatek: use BIT() to instead of SPI_CMD_*_OFFSET
  spi: medaitek: revise quirks compatibility style
  spi: mediatek: fix spi incorrect endian usage
  ...
parents cf9d615f c5992f61

Documentation/devicetree/bindings/powerpc/fsl/mpc5121-psc.txt

+18 −6
Original line number Diff line number Diff line
@@ -6,14 +6,14 @@ PSC in UART mode 
For PSC in UART mode the needed PSC serial devices

are specified by fsl,mpc5121-psc-uart nodes in the

fsl,mpc5121-immr SoC node. Additionally the PSC FIFO

Controller node fsl,mpc5121-psc-fifo is requered there:

Controller node fsl,mpc5121-psc-fifo is required there:



fsl,mpc5121-psc-uart nodes

fsl,mpc512x-psc-uart nodes

--------------------------



Required properties :

 - compatible : Should contain "fsl,mpc5121-psc-uart" and "fsl,mpc5121-psc"

 - cell-index : Index of the PSC in hardware

 - compatible : Should contain "fsl,<soc>-psc-uart" and "fsl,<soc>-psc"

   Supported <soc>s: mpc5121, mpc5125

 - reg : Offset and length of the register set for the PSC device

 - interrupts : <a b> where a is the interrupt number of the

   PSC FIFO Controller and b is a field that represents an
@@ -25,12 +25,21 @@ Recommended properties : 
 - fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4)

 - fsl,tx-fifo-size : the size of the TX fifo slice (a multiple of 4)



PSC in SPI mode

---------------



fsl,mpc5121-psc-fifo node

Similar to the UART mode a PSC can be operated in SPI mode. The compatible used

for that is fsl,mpc5121-psc-spi. It requires a fsl,mpc5121-psc-fifo as well.

The required and recommended properties are identical to the

fsl,mpc5121-psc-uart nodes, just use spi instead of uart in the compatible

string.



fsl,mpc512x-psc-fifo node

-------------------------



Required properties :

 - compatible : Should be "fsl,mpc5121-psc-fifo"

 - compatible : Should be "fsl,<soc>-psc-fifo"

   Supported <soc>s: mpc5121, mpc5125

 - reg : Offset and length of the register set for the PSC

         FIFO Controller

 - interrupts : <a b> where a is the interrupt number of the
@@ -39,6 +48,9 @@ Required properties : 
 - interrupt-parent : the phandle for the interrupt controller that

   services interrupts for this device.



Recommended properties :

 - clocks : specifies the clock needed to operate the fifo controller

 - clock-names : name(s) for the clock(s) listed in clocks



Example for a board using PSC0 and PSC1 devices in serial mode:

Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt

+2 −0
Original line number Diff line number Diff line
@@ -10,6 +10,8 @@ Required properties: 
Optional properties:

- cs-gpios : Specifies the gpio pis to be used for chipselects.

- num-cs : The number of chipselects. If omitted, this will default to 4.

- reg-io-width : The I/O register width (in bytes) implemented by this

  device.  Supported values are 2 or 4 (the default).



Child nodes as per the generic SPI binding.

Documentation/devicetree/bindings/spi/spi-davinci.txt

+2 −0
Original line number Diff line number Diff line
@@ -12,6 +12,8 @@ Required properties: 
- compatible:

	- "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family

	- "ti,da830-spi" for SPI used similar to that on DA8xx SoC family

	- "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC

		family

- reg: Offset and length of SPI controller register space

- num-cs: Number of chip selects. This includes internal as well as

	GPIO chip selects.

Documentation/devicetree/bindings/spi/spi-img-spfi.txt

+1 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ Required properties: 
Optional properties:

- img,supports-quad-mode: Should be set if the interface supports quad mode

  SPI transfers.

- spfi-max-frequency: Maximum speed supported by the spfi block.



Example:

Documentation/devicetree/bindings/spi/spi-mt65xx.txt

0 → 100644
+51 −0
Original line number Diff line number Diff line 
Binding for MTK SPI controller



Required properties:

- compatible: should be one of the following.

    - mediatek,mt8173-spi: for mt8173 platforms

    - mediatek,mt8135-spi: for mt8135 platforms

    - mediatek,mt6589-spi: for mt6589 platforms



- #address-cells: should be 1.



- #size-cells: should be 0.



- reg: Address and length of the register set for the device



- interrupts: Should contain spi interrupt



- clocks: phandles to input clocks.

  The first should be <&topckgen CLK_TOP_SPI_SEL>.

  The second should be one of the following.

   -  <&clk26m>: specify parent clock 26MHZ.

   -  <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ.

				      It's the default one.

   -  <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ.

   -  <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.

   -  <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.



- clock-names: shall be "spi-clk" for the controller clock, and

  "parent-clk" for the parent clock.



Optional properties:

- mediatek,pad-select: specify which pins group(ck/mi/mo/cs) spi

  controller used, this value should be 0~3, only required for MT8173.

    0: specify GPIO69,70,71,72 for spi pins.

    1: specify GPIO102,103,104,105 for spi pins.

    2: specify GPIO128,129,130,131 for spi pins.

    3: specify GPIO5,6,7,8 for spi pins.



Example:



- SoC Specific Portion:

spi: spi@1100a000 {

	compatible = "mediatek,mt8173-spi";

	#address-cells = <1>;

	#size-cells = <0>;

	reg = <0 0x1100a000 0 0x1000>;

	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;

	clocks = <&topckgen CLK_TOP_SPI_SEL>, <&topckgen CLK_TOP_SYSPLL3_D2>;

	clock-names = "spi-clk", "parent-clk";

	mediatek,pad-select = <0>;

	status = "disabled";

};

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