Commit e5a32b5b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mips_4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux 

Pull MIPS updates from Paul Burton:
 "Here are the main MIPS changes for 4.19.

  An overview of the general architecture changes:

   - Massive DMA ops refactoring from Christoph Hellwig (huzzah for
     deleting crufty code!).

   - We introduce NT_MIPS_DSP & NT_MIPS_FP_MODE ELF notes &
     corresponding regsets to expose DSP ASE & floating point mode state
     respectively, both for live debugging & core dumps.

   - We better optimize our code by hard-coding cpu_has_* macros at
     compile time where their values are known due to the ISA revision
     that the kernel build is targeting.

   - The EJTAG exception handler now better handles SMP systems, where
     it was previously possible for CPUs to clobber a register value
     saved by another CPU.

   - Our implementation of memset() gained a couple of fixes for MIPSr6
     systems to return correct values in some cases where stores fault.

   - We now implement ioremap_wc() using the uncached-accelerated cache
     coherency attribute where supported, which is detected during boot,
     and fall back to plain uncached access where necessary. The
     MIPS-specific (and unused in tree) ioremap_uncached_accelerated() &
     ioremap_cacheable_cow() are removed.

   - The prctl(PR_SET_FP_MODE, ...) syscall is better supported for SMP
     systems by reworking the way we ensure remote CPUs that may be
     running threads within the affected process switch mode.

   - Systems using the MIPS Coherence Manager will now set the
     MIPS_IC_SNOOPS_REMOTE flag to avoid some unnecessary cache
     maintenance overhead when flushing the icache.

   - A few fixes were made for building with clang/LLVM, which now
     sucessfully builds kernels for many of our platforms.

   - Miscellaneous cleanups all over.

  And some platform-specific changes:

   - ar7 gained stubs for a few clock API functions to fix build
     failures for some drivers.

   - ath79 gained support for a few new SoCs, a few fixes & better
     gpio-keys support.

   - Ci20 now exposes its SPI bus using the spi-gpio driver.

   - The generic platform can now auto-detect a suitable value for
     PHYS_OFFSET based upon the memory map described by the device tree,
     allowing us to avoid wasting memory on page book-keeping for
     systems where RAM starts at a non-zero physical address.

   - Ingenic systems using the jz4740 platform code now link their
     vmlinuz higher to allow for kernels of a realistic size.

   - Loongson32 now builds the kernel targeting MIPSr1 rather than
     MIPSr2 to avoid CPU errata.

   - Loongson64 gains a couple of fixes, a workaround for a write
     buffering issue & support for the Loongson 3A R3.1 CPU.

   - Malta now uses the piix4-poweroff driver to handle powering down.

   - Microsemi Ocelot gained support for its SPI bus & NOR flash, its
     second MDIO bus and can now be supported by a FIT/.itb image.

   - Octeon saw a bunch of header cleanups which remove a lot of
     duplicate or unused code"

* tag 'mips_4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (123 commits)
  MIPS: Remove remnants of UASM_ISA
  MIPS: netlogic: xlr: Remove erroneous check in nlm_fmn_send()
  MIPS: VDSO: Force link endianness
  MIPS: Always specify -EB or -EL when using clang
  MIPS: Use dins to simplify __write_64bit_c0_split()
  MIPS: Use read-write output operand in __write_64bit_c0_split()
  MIPS: Avoid using array as parameter to write_c0_kpgd()
  MIPS: vdso: Allow clang's --target flag in VDSO cflags
  MIPS: genvdso: Remove GOT checks
  MIPS: Remove obsolete MIPS checks for DST node "chosen@0"
  MIPS: generic: Remove input symbols from defconfig
  MIPS: Delete unused code in linux32.c
  MIPS: Remove unused sys_32_mmap2
  MIPS: Remove nabi_no_regargs
  mips: dts: mscc: enable spi and NOR flash support on ocelot PCB123
  mips: dts: mscc: Add spi on Ocelot
  MIPS: Loongson: Merge load addresses
  MIPS: Loongson: Set Loongson32 to MIPS32R1
  MIPS: mscc: ocelot: add interrupt controller properties to GPIO controller
  MIPS: generic: Select MIPS_AUTO_PFN_OFFSET
  ...
parents 2280a536 22f20a11

Documentation/devicetree/bindings/phy/phy-ath79-usb.txt

+2 −2
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 
Required properties:

- compatible: "qca,ar7100-usb-phy"

- #phys-cells: should be 0

- reset-names: "usb-phy"[, "usb-suspend-override"]

- reset-names: "phy"[, "suspend-override"]

- resets: references to the reset controllers



Example:
@@ -11,7 +11,7 @@ Example: 
	usb-phy {

		compatible = "qca,ar7100-usb-phy";



		reset-names = "usb-phy", "usb-suspend-override";

		reset-names = "phy", "suspend-override";

		resets = <&rst 4>, <&rst 3>;



		#phy-cells = <0>;

arch/mips/Kconfig

+28 −28
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ config MIPS 
	select BUILDTIME_EXTABLE_SORT

	select CLONE_BACKWARDS

	select CPU_PM if CPU_IDLE

	select DMA_DIRECT_OPS

	select GENERIC_ATOMIC64 if !64BIT

	select GENERIC_CLOCKEVENTS

	select GENERIC_CMOS_UPDATE
@@ -97,6 +98,7 @@ config MIPS_GENERIC 
	select HW_HAS_PCI

	select IRQ_MIPS_CPU

	select LIBFDT

	select MIPS_AUTO_PFN_OFFSET

	select MIPS_CPU_SCACHE

	select MIPS_GIC

	select MIPS_L1_CACHE_SHIFT_7
@@ -193,6 +195,7 @@ config ATH79 
	select CSRC_R4K

	select DMA_NONCOHERENT

	select GPIOLIB

	select PINCTRL

	select HAVE_CLK

	select COMMON_CLK

	select CLKDEV_LOOKUP
@@ -211,6 +214,8 @@ config ATH79 


config BMIPS_GENERIC

	bool "Broadcom Generic BMIPS kernel"

	select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL

	select ARCH_HAS_PHYS_TO_DMA

	select BOOT_RAW

	select NO_EXCEPT_FILL

	select USE_OF
@@ -438,7 +443,6 @@ config MACH_LOONGSON32 


config MACH_LOONGSON64

	bool "Loongson-2/3 family of machines"

	select ARCH_HAS_PHYS_TO_DMA

	select SYS_SUPPORTS_ZBOOT

	help

	  This enables the support of Loongson-2/3 family of machines.
@@ -662,11 +666,11 @@ config SGI_IP22 


config SGI_IP27

	bool "SGI IP27 (Origin200/2000)"

	select ARCH_HAS_PHYS_TO_DMA

	select FW_ARC

	select FW_ARC64

	select BOOT_ELF64

	select DEFAULT_SGI_PARTITION

	select DMA_COHERENT

	select SYS_HAS_EARLY_PRINTK

	select HW_HAS_PCI

	select NR_CPUS_DEFAULT_64
@@ -721,6 +725,7 @@ config SGI_IP28 


config SGI_IP32

	bool "SGI IP32 (O2)"

	select ARCH_HAS_PHYS_TO_DMA

	select FW_ARC

	select FW_ARC32

	select BOOT_ELF32
@@ -743,7 +748,6 @@ config SGI_IP32 
config SIBYTE_CRHINE

	bool "Sibyte BCM91120C-CRhine"

	select BOOT_ELF32

	select DMA_COHERENT

	select SIBYTE_BCM1120

	select SWAP_IO_SPACE

	select SYS_HAS_CPU_SB1
@@ -753,7 +757,6 @@ config SIBYTE_CRHINE 
config SIBYTE_CARMEL

	bool "Sibyte BCM91120x-Carmel"

	select BOOT_ELF32

	select DMA_COHERENT

	select SIBYTE_BCM1120

	select SWAP_IO_SPACE

	select SYS_HAS_CPU_SB1
@@ -763,7 +766,6 @@ config SIBYTE_CARMEL 
config SIBYTE_CRHONE

	bool "Sibyte BCM91125C-CRhone"

	select BOOT_ELF32

	select DMA_COHERENT

	select SIBYTE_BCM1125

	select SWAP_IO_SPACE

	select SYS_HAS_CPU_SB1
@@ -774,7 +776,6 @@ config SIBYTE_CRHONE 
config SIBYTE_RHONE

	bool "Sibyte BCM91125E-Rhone"

	select BOOT_ELF32

	select DMA_COHERENT

	select SIBYTE_BCM1125H

	select SWAP_IO_SPACE

	select SYS_HAS_CPU_SB1
@@ -784,7 +785,6 @@ config SIBYTE_RHONE 
config SIBYTE_SWARM

	bool "Sibyte BCM91250A-SWARM"

	select BOOT_ELF32

	select DMA_COHERENT

	select HAVE_PATA_PLATFORM

	select SIBYTE_SB1250

	select SWAP_IO_SPACE
@@ -797,7 +797,6 @@ config SIBYTE_SWARM 
config SIBYTE_LITTLESUR

	bool "Sibyte BCM91250C2-LittleSur"

	select BOOT_ELF32

	select DMA_COHERENT

	select HAVE_PATA_PLATFORM

	select SIBYTE_SB1250

	select SWAP_IO_SPACE
@@ -809,7 +808,6 @@ config SIBYTE_LITTLESUR 
config SIBYTE_SENTOSA

	bool "Sibyte BCM91250E-Sentosa"

	select BOOT_ELF32

	select DMA_COHERENT

	select SIBYTE_SB1250

	select SWAP_IO_SPACE

	select SYS_HAS_CPU_SB1
@@ -819,7 +817,6 @@ config SIBYTE_SENTOSA 
config SIBYTE_BIGSUR

	bool "Sibyte BCM91480B-BigSur"

	select BOOT_ELF32

	select DMA_COHERENT

	select NR_CPUS_DEFAULT_4

	select SIBYTE_BCM1x80

	select SWAP_IO_SPACE
@@ -895,8 +892,8 @@ config CAVIUM_OCTEON_SOC 
	bool "Cavium Networks Octeon SoC based boards"

	select CEVT_R4K

	select ARCH_HAS_PHYS_TO_DMA

	select HAS_RAPIDIO

	select PHYS_ADDR_T_64BIT

	select DMA_COHERENT

	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select EDAC_SUPPORT
@@ -945,7 +942,6 @@ config NLM_XLR_BOARD 
	select PHYS_ADDR_T_64BIT

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_HIGHMEM

	select DMA_COHERENT

	select NR_CPUS_DEFAULT_32

	select CEVT_R4K

	select CSRC_R4K
@@ -973,7 +969,6 @@ config NLM_XLP_BOARD 
	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SYS_SUPPORTS_HIGHMEM

	select DMA_COHERENT

	select NR_CPUS_DEFAULT_32

	select CEVT_R4K

	select CSRC_R4K
@@ -992,7 +987,6 @@ config MIPS_PARAVIRT 
	bool "Para-Virtualized guest system"

	select CEVT_R4K

	select CSRC_R4K

	select DMA_COHERENT

	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN
@@ -1118,12 +1112,14 @@ config DMA_PERDEV_COHERENT 
	bool

	select DMA_MAYBE_COHERENT



config DMA_COHERENT

	bool



config DMA_NONCOHERENT

	bool

	select ARCH_HAS_SYNC_DMA_FOR_DEVICE

	select ARCH_HAS_SYNC_DMA_FOR_CPU

	select NEED_DMA_MAP_STATE

	select DMA_NONCOHERENT_MMAP

	select DMA_NONCOHERENT_CACHE_SYNC

	select DMA_NONCOHERENT_OPS



config SYS_HAS_EARLY_PRINTK

	bool
@@ -1365,6 +1361,7 @@ choice 
config CPU_LOONGSON3

	bool "Loongson 3 CPU"

	depends on SYS_HAS_CPU_LOONGSON3

	select ARCH_HAS_PHYS_TO_DMA

	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM

	select CPU_SUPPORTS_HUGEPAGES
@@ -1427,7 +1424,8 @@ config CPU_LOONGSON1B 
	select LEDS_GPIO_REGISTER

	help

	  The Loongson 1B is a 32-bit SoC, which implements the MIPS32

	  release 2 instruction set.

	  Release 1 instruction set and part of the MIPS32 Release 2

	  instruction set.



config CPU_LOONGSON1C

	bool "Loongson 1C"
@@ -1436,7 +1434,8 @@ config CPU_LOONGSON1C 
	select LEDS_GPIO_REGISTER

	help

	  The Loongson 1C is a 32-bit SoC, which implements the MIPS32

	  release 2 instruction set.

	  Release 1 instruction set and part of the MIPS32 Release 2

	  instruction set.



config CPU_MIPS32_R1

	bool "MIPS32 Release 1"
@@ -1831,11 +1830,12 @@ config CPU_LOONGSON2 
	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM

	select CPU_SUPPORTS_HUGEPAGES

	select ARCH_HAS_PHYS_TO_DMA



config CPU_LOONGSON1

	bool

	select CPU_MIPS32

	select CPU_MIPSR2

	select CPU_MIPSR1

	select CPU_HAS_PREFETCH

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM
@@ -1979,12 +1979,6 @@ config SYS_HAS_CPU_XLR 
config SYS_HAS_CPU_XLP

	bool



config MIPS_MALTA_PM

	depends on MIPS_MALTA

	depends on PCI

	bool

	default y



#

# CPU may reorder R->R, R->W, W->R, W->W

# Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
@@ -2994,6 +2988,9 @@ config PGTABLE_LEVELS 
	default 3 if 64BIT && !PAGE_SIZE_64KB

	default 2



config MIPS_AUTO_PFN_OFFSET

	bool



source "init/Kconfig"



source "kernel/Kconfig.freezer"
@@ -3115,10 +3112,13 @@ config ZONE_DMA32 


source "drivers/pcmcia/Kconfig"



config HAS_RAPIDIO

	bool

	default n



config RAPIDIO

	tristate "RapidIO support"

	depends on PCI

	default n

	depends on HAS_RAPIDIO || PCI

	help

	  If you say Y here, the kernel will include drivers and

	  infrastructure code to support RapidIO interconnect devices.

arch/mips/Makefile

+14 −8
Original line number Diff line number Diff line
@@ -122,12 +122,22 @@ cflags-y += -ffreestanding 
# are used, so we kludge that here.  A bug has been filed at

# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=29413.

#

# clang doesn't suffer from these issues and our checks against -dumpmachine

# don't work so well when cross compiling, since without providing --target

# clang's output will be based upon the build machine. So for clang we simply

# unconditionally specify -EB or -EL as appropriate.

#

ifeq ($(cc-name),clang)

cflags-$(CONFIG_CPU_BIG_ENDIAN)		+= -EB

cflags-$(CONFIG_CPU_LITTLE_ENDIAN)	+= -EL

else

undef-all += -UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__

undef-all += -UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__

predef-be += -DMIPSEB -D_MIPSEB -D__MIPSEB -D__MIPSEB__

predef-le += -DMIPSEL -D_MIPSEL -D__MIPSEL -D__MIPSEL__

cflags-$(CONFIG_CPU_BIG_ENDIAN)		+= $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' && echo -EB $(undef-all) $(predef-be))

cflags-$(CONFIG_CPU_LITTLE_ENDIAN)	+= $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL $(undef-all) $(predef-le))

endif



cflags-$(CONFIG_SB1XXX_CORELIS)	+= $(call cc-option,-mno-sched-prolog) \

				   -fno-omit-frame-pointer
@@ -155,15 +165,11 @@ cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap 
cflags-$(CONFIG_CPU_VR41XX)	+= -march=r4100 -Wa,--trap

cflags-$(CONFIG_CPU_R4X00)	+= -march=r4600 -Wa,--trap

cflags-$(CONFIG_CPU_TX49XX)	+= -march=r4600 -Wa,--trap

cflags-$(CONFIG_CPU_MIPS32_R1)	+= $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \

			-Wa,-mips32 -Wa,--trap

cflags-$(CONFIG_CPU_MIPS32_R2)	+= $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \

			-Wa,-mips32r2 -Wa,--trap

cflags-$(CONFIG_CPU_MIPS32_R1)	+= -march=mips32 -Wa,--trap

cflags-$(CONFIG_CPU_MIPS32_R2)	+= -march=mips32r2 -Wa,--trap

cflags-$(CONFIG_CPU_MIPS32_R6)	+= -march=mips32r6 -Wa,--trap -modd-spreg

cflags-$(CONFIG_CPU_MIPS64_R1)	+= $(call cc-option,-march=mips64,-mips64 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) \

			-Wa,-mips64 -Wa,--trap

cflags-$(CONFIG_CPU_MIPS64_R2)	+= $(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) \

			-Wa,-mips64r2 -Wa,--trap

cflags-$(CONFIG_CPU_MIPS64_R1)	+= -march=mips64 -Wa,--trap

cflags-$(CONFIG_CPU_MIPS64_R2)	+= -march=mips64r2 -Wa,--trap

cflags-$(CONFIG_CPU_MIPS64_R6)	+= -march=mips64r6 -Wa,--trap

cflags-$(CONFIG_CPU_R5000)	+= -march=r5000 -Wa,--trap

cflags-$(CONFIG_CPU_R5432)	+= $(call cc-option,-march=r5400,-march=r5000) \

arch/mips/alchemy/board-gpr.c

+2 −1
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ 
#include <asm/bootinfo.h>

#include <asm/idle.h>

#include <asm/reboot.h>

#include <asm/setup.h>

#include <asm/mach-au1x00/au1000.h>

#include <asm/mach-au1x00/gpio-au1000.h>

#include <prom.h>
@@ -60,7 +61,7 @@ void __init prom_init(void) 
	add_memory_region(0, memsize, BOOT_MEM_RAM);

}



void prom_putchar(unsigned char c)

void prom_putchar(char c)

{

	alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);

}

arch/mips/alchemy/board-mtx1.c

+2 −1
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 
#include <mtd/mtd-abi.h>

#include <asm/bootinfo.h>

#include <asm/reboot.h>

#include <asm/setup.h>

#include <asm/mach-au1x00/au1000.h>

#include <asm/mach-au1x00/gpio-au1000.h>

#include <asm/mach-au1x00/au1xxx_eth.h>
@@ -58,7 +59,7 @@ void __init prom_init(void) 
	add_memory_region(0, memsize, BOOT_MEM_RAM);

}



void prom_putchar(unsigned char c)

void prom_putchar(char c)

{

	alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);

}

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