Commit e57253a8 authored by Suresh Siddha's avatar Suresh Siddha Committed by Ingo Molnar
Browse files

x86, ioapic: Restore the mask bit correctly in eoi_ioapic_irq() 



For older IO-APIC's, we were clearing the remote-IRR by changing
the RTE trigger mode to edge and then back to level. We wanted
to mask the RTE during this process, so we were essentially
doing mask+edge and then to unmask+level.

As part of the commit ca64c47c,
we moved this EOI process earlier where the IO-APIC RTE is
masked. So we were wrongly unmasking it in the eoi_ioapic_irq().

So change the remote-IRR clear sequence in eoi_ioapic_irq() to
mask + edge and then restore the previous RTE entry which will
restore the mask status as well as the level trigger.

Signed-off-by: default avatarSuresh Siddha <suresh.b.siddha@intel.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: Thomas Renninger <trenn@suse.de>
Cc: Rafael Wysocki <rjw@novell.com>
Cc: lchiquitto@novell.com
Cc: jbeulich@novell.com
Cc: yinghai@kernel.org
Link: http://lkml.kernel.org/r/20110825190657.210286410@sbsiddha-desk.sc.intel.com


Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 1e75b31d

arch/x86/kernel/apic/io_apic.c

+27 −16
Original line number Diff line number Diff line
@@ -394,13 +394,21 @@ union entry_union { 
	struct IO_APIC_route_entry entry;

};



static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)

{

	union entry_union eu;



	eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);

	eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);

	return eu.entry;

}



static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)

{

	union entry_union eu;

	unsigned long flags;

	raw_spin_lock_irqsave(&ioapic_lock, flags);

	eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);

	eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);

	eu.entry = __ioapic_read_entry(apic, pin);

	raw_spin_unlock_irqrestore(&ioapic_lock, flags);

	return eu.entry;

}
@@ -529,18 +537,6 @@ static void io_apic_modify_irq(struct irq_cfg *cfg, 
		__io_apic_modify_irq(entry, mask_and, mask_or, final);

}



static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry)

{

	__io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER,

			     IO_APIC_REDIR_MASKED, NULL);

}



static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry)

{

	__io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED,

			     IO_APIC_REDIR_LEVEL_TRIGGER, NULL);

}



static void io_apic_sync(struct irq_pin_list *entry)

{

	/*
@@ -2496,8 +2492,23 @@ static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) 
			else

				io_apic_eoi(entry->apic, cfg->vector);

		} else {

			__mask_and_edge_IO_APIC_irq(entry);

			__unmask_and_level_IO_APIC_irq(entry);

			struct IO_APIC_route_entry rte, rte1;



			rte = rte1 =

				__ioapic_read_entry(entry->apic, entry->pin);



			/*

			 * Mask the entry and change the trigger mode to edge.

			 */

			rte1.mask = 1;

			rte1.trigger = IOAPIC_EDGE;



			__ioapic_write_entry(apic, pin, rte1);



			/*

			 * Restore the previous level triggered entry.

			 */

			__ioapic_write_entry(apic, pin, rte);

		}

	}

	raw_spin_unlock_irqrestore(&ioapic_lock, flags);

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