Commit e56c60c3 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'zynq-clk-for-3.11' of git://git.xilinx.com/linux-xlnx into next/soc 

From Michal Simek:
arm: Xilinx Zynq clock changes for v3.11

Change Xilinx Zynq DT clock description which reflects logical abstraction
of Zynq's clock tree.

- Refactor PLL driver
- Use new clock controller driver
- Change timer and uart drivers

* tag 'zynq-clk-for-3.11' of git://git.xilinx.com/linux-xlnx

:
  clk: zynq: Remove deprecated clock code
  arm: zynq: Migrate platform to clock controller
  clk: zynq: Add clock controller driver
  clk: zynq: Factor out PLL driver

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents f4902492 97c4e87d

Documentation/devicetree/bindings/clock/zynq-7000.txt

+86 −37
Original line number Diff line number Diff line
@@ -6,50 +6,99 @@ The purpose of this document is to document their usage. 
See clock_bindings.txt for more information on the generic clock bindings.

See Chapter 25 of Zynq TRM for more information about Zynq clocks.



== PLLs ==



Used to describe the ARM_PLL, DDR_PLL, and IO_PLL.

== Clock Controller ==

The clock controller is a logical abstraction of Zynq's clock tree. It reads

required input clock frequencies from the devicetree and acts as clock provider

for all clock consumers of PS clocks.



Required properties:

- #clock-cells : shall be 0 (only one clock is output from this node)

- compatible : "xlnx,zynq-pll"

- reg : pair of u32 values, which are the address offsets within the SLCR

        of the relevant PLL_CTRL register and PLL_CFG register respectively

- clocks : phandle for parent clock.  should be the phandle for ps_clk

 - #clock-cells : Must be 1

 - compatible : "xlnx,ps7-clkc"

 - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ

		      (usually 33 MHz oscillators are used for Zynq platforms)

 - clock-output-names : List of strings used to name the clock outputs. Shall be

			a list of the outputs given below.



Optional properties:

- clock-output-names : name of the output clock



Example:

	armpll: armpll {

		#clock-cells = <0>;

		compatible = "xlnx,zynq-pll";

		clocks = <&ps_clk>;

		reg = <0x100 0x110>;

		clock-output-names = "armpll";

	};



== Peripheral clocks ==

 - clocks : as described in the clock bindings

 - clock-names : as described in the clock bindings



Describes clock node for the SDIO, SMC, SPI, QSPI, and UART clocks.

Clock inputs:

The following strings are optional parameters to the 'clock-names' property in

order to provide an optional (E)MIO clock source.

 - swdt_ext_clk

 - gem0_emio_clk

 - gem1_emio_clk

 - mio_clk_XX		# with XX = 00..53

...



Required properties:

- #clock-cells : shall be 1

- compatible : "xlnx,zynq-periph-clock"

- reg : a single u32 value, describing the offset within the SLCR where

        the CLK_CTRL register is found for this peripheral

- clocks : phandle for parent clocks.  should hold phandles for

           the IO_PLL, ARM_PLL, and DDR_PLL in order

- clock-output-names : names of the output clock(s).  For peripherals that have

                       two output clocks (for example, the UART), two clocks

                       should be listed.

Clock outputs:

 0:  armpll

 1:  ddrpll

 2:  iopll

 3:  cpu_6or4x

 4:  cpu_3or2x

 5:  cpu_2x

 6:  cpu_1x

 7:  ddr2x

 8:  ddr3x

 9:  dci

 10: lqspi

 11: smc

 12: pcap

 13: gem0

 14: gem1

 15: fclk0

 16: fclk1

 17: fclk2

 18: fclk3

 19: can0

 20: can1

 21: sdio0

 22: sdio1

 23: uart0

 24: uart1

 25: spi0

 26: spi1

 27: dma

 28: usb0_aper

 29: usb1_aper

 30: gem0_aper

 31: gem1_aper

 32: sdio0_aper

 33: sdio1_aper

 34: spi0_aper

 35: spi1_aper

 36: can0_aper

 37: can1_aper

 38: i2c0_aper

 39: i2c1_aper

 40: uart0_aper

 41: uart1_aper

 42: gpio_aper

 43: lqspi_aper

 44: smc_aper

 45: swdt

 46: dbg_trc

 47: dbg_apb



Example:

	uart_clk: uart_clk {

	clkc: clkc {

		#clock-cells = <1>;

		compatible = "xlnx,zynq-periph-clock";

		clocks = <&iopll &armpll &ddrpll>;

		reg = <0x154>;

		clock-output-names = "uart0_ref_clk",

				     "uart1_ref_clk";

		compatible = "xlnx,ps7-clkc";

		ps-clk-frequency = <33333333>;

		clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",

				"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",

				"dci", "lqspi", "smc", "pcap", "gem0", "gem1",

				"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",

				"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",

				"dma", "usb0_aper", "usb1_aper", "gem0_aper",

				"gem1_aper", "sdio0_aper", "sdio1_aper",

				"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",

				"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",

				"gpio_aper", "lqspi_aper", "smc_aper", "swdt",

				"dbg_trc", "dbg_apb";

		# optional props

		clocks = <&clkc 16>, <&clk_foo>;

		clock-names = "gem1_emio_clk", "can_mio_clk_23";

	};

arch/arm/boot/dts/zynq-7000.dtsi

+21 −50
Original line number Diff line number Diff line
@@ -49,16 +49,18 @@ 


		uart0: uart@e0000000 {

			compatible = "xlnx,xuartps";

			clocks = <&clkc 23>, <&clkc 40>;

			clock-names = "ref_clk", "aper_clk";

			reg = <0xE0000000 0x1000>;

			interrupts = <0 27 4>;

			clocks = <&uart_clk 0>;

		};



		uart1: uart@e0001000 {

			compatible = "xlnx,xuartps";

			clocks = <&clkc 24>, <&clkc 41>;

			clock-names = "ref_clk", "aper_clk";

			reg = <0xE0001000 0x1000>;

			interrupts = <0 50 4>;

			clocks = <&uart_clk 1>;

		};



		slcr: slcr@f8000000 {
@@ -69,50 +71,21 @@ 
				#address-cells = <1>;

				#size-cells = <0>;



				ps_clk: ps_clk {

					#clock-cells = <0>;

					compatible = "fixed-clock";

					/* clock-frequency set in board-specific file */

					clock-output-names = "ps_clk";

				};

				armpll: armpll {

					#clock-cells = <0>;

					compatible = "xlnx,zynq-pll";

					clocks = <&ps_clk>;

					reg = <0x100 0x110>;

					clock-output-names = "armpll";

				};

				ddrpll: ddrpll {

					#clock-cells = <0>;

					compatible = "xlnx,zynq-pll";

					clocks = <&ps_clk>;

					reg = <0x104 0x114>;

					clock-output-names = "ddrpll";

				};

				iopll: iopll {

					#clock-cells = <0>;

					compatible = "xlnx,zynq-pll";

					clocks = <&ps_clk>;

					reg = <0x108 0x118>;

					clock-output-names = "iopll";

				};

				uart_clk: uart_clk {

					#clock-cells = <1>;

					compatible = "xlnx,zynq-periph-clock";

					clocks = <&iopll &armpll &ddrpll>;

					reg = <0x154>;

					clock-output-names = "uart0_ref_clk",

							     "uart1_ref_clk";

				};

				cpu_clk: cpu_clk {

				clkc: clkc {

					#clock-cells = <1>;

					compatible = "xlnx,zynq-cpu-clock";

					clocks = <&iopll &armpll &ddrpll>;

					reg = <0x120 0x1C4>;

					clock-output-names = "cpu_6x4x",

							     "cpu_3x2x",

							     "cpu_2x",

							     "cpu_1x";

					compatible = "xlnx,ps7-clkc";

					ps-clk-frequency = <33333333>;

					clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",

							"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",

							"dci", "lqspi", "smc", "pcap", "gem0", "gem1",

							"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",

							"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",

							"dma", "usb0_aper", "usb1_aper", "gem0_aper",

							"gem1_aper", "sdio0_aper", "sdio1_aper",

							"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",

							"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",

							"gpio_aper", "lqspi_aper", "smc_aper", "swdt",

							"dbg_trc", "dbg_apb";

				};

			};

		};
@@ -121,9 +94,8 @@ 
			interrupt-parent = <&intc>;

			interrupts = < 0 10 4 0 11 4 0 12 4 >;

			compatible = "cdns,ttc";

			clocks = <&clkc 6>;

			reg = <0xF8001000 0x1000>;

			clocks = <&cpu_clk 3>;

			clock-names = "cpu_1x";

			clock-ranges;

		};
@@ -131,9 +103,8 @@ 
			interrupt-parent = <&intc>;

			interrupts = < 0 37 4 0 38 4 0 39 4 >;

			compatible = "cdns,ttc";

			clocks = <&clkc 6>;

			reg = <0xF8002000 0x1000>;

			clocks = <&cpu_clk 3>;

			clock-names = "cpu_1x";

			clock-ranges;

		};

		scutimer: scutimer@f8f00600 {
@@ -141,7 +112,7 @@ 
			interrupts = < 1 13 0x301 >;

			compatible = "arm,cortex-a9-twd-timer";

			reg = < 0xf8f00600 0x20 >;

			clocks = <&cpu_clk 1>;

			clocks = <&clkc 4>;

		} ;

	};

};

arch/arm/boot/dts/zynq-zc702.dts

+0 −4
Original line number Diff line number Diff line
@@ -28,7 +28,3 @@ 
	};



};
 


&ps_clk {

	clock-frequency = <33333330>;

};

arch/arm/mach-zynq/slcr.c

+1 −1
Original line number Diff line number Diff line
@@ -117,7 +117,7 @@ int __init zynq_slcr_init(void) 


	pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);



	xilinx_zynq_clocks_init(zynq_slcr_base);

	zynq_clock_init(zynq_slcr_base);



	of_node_put(np);

drivers/clk/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -27,7 +27,7 @@ obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o 
obj-$(CONFIG_ARCH_SUNXI)	+= sunxi/

obj-$(CONFIG_ARCH_U8500)	+= ux500/

obj-$(CONFIG_ARCH_VT8500)	+= clk-vt8500.o

obj-$(CONFIG_ARCH_ZYNQ)		+= clk-zynq.o

obj-$(CONFIG_ARCH_ZYNQ)		+= zynq/

obj-$(CONFIG_ARCH_TEGRA)	+= tegra/

obj-$(CONFIG_PLAT_SAMSUNG)	+= samsung/

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