Commit e518634b authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/dsi: use vlv and bxt prefixes for the global DSI functions 

Avoid confusion with the functions to be added for the new ICL or gen 11
DSI implementation by renaming the current DSI functions. While at it,
permutate the words in the function names to make them all start with
"vlv_dsi" or "vlv_dsi_pll" etc.

Reduce the platform abstractions in the PLL file while at it, moving the
checks to vlv_dsi.c instead, where we typically already have the
necessary if ladders.

Leave the static functions as-is for now; they could be renamed later if
needed.

No functional changes.

v2: use "gen7" prefix.

v3: use "vlv" and "bxt" prefixes, reduce the abstractions.

References: https://patchwork.freedesktop.org/series/44823/


Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarMadhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180705132509.12881-2-jani.nikula@intel.com
parent ca3589c1

drivers/gpu/drm/i915/intel_display.c

+3 −3
Original line number Diff line number Diff line
@@ -9416,7 +9416,7 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, 
		 * registers/MIPI[BXT]. We can break out here early, since we

		 * need the same DSI PLL to be enabled for both DSI ports.

		 */

		if (!intel_dsi_pll_is_enabled(dev_priv))

		if (!bxt_dsi_pll_is_enabled(dev_priv))

			break;



		/* XXX: this works for video mode only */
@@ -14092,7 +14092,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) 
		intel_ddi_init(dev_priv, PORT_B);

		intel_ddi_init(dev_priv, PORT_C);



		intel_dsi_init(dev_priv);

		vlv_dsi_init(dev_priv);

	} else if (HAS_DDI(dev_priv)) {

		int found;
@@ -14198,7 +14198,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) 
				intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);

		}



		intel_dsi_init(dev_priv);

		vlv_dsi_init(dev_priv);

	} else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {

		bool found = false;

drivers/gpu/drm/i915/intel_drv.h

+1 −1
Original line number Diff line number Diff line
@@ -1731,7 +1731,7 @@ int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector); 
int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);

void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);

/* vlv_dsi.c */

void intel_dsi_init(struct drm_i915_private *dev_priv);

void vlv_dsi_init(struct drm_i915_private *dev_priv);



/* intel_dsi_dcs_backlight.c */

int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);

drivers/gpu/drm/i915/intel_dsi.h

+19 −11
Original line number Diff line number Diff line
@@ -130,20 +130,28 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder) 
}



/* vlv_dsi.c */

void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port);

void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);

enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);



/* vlv_dsi_pll.c */

bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv);

int intel_compute_dsi_pll(struct intel_encoder *encoder,

int vlv_dsi_pll_compute(struct intel_encoder *encoder,

			struct intel_crtc_state *config);

void intel_enable_dsi_pll(struct intel_encoder *encoder,

void vlv_dsi_pll_enable(struct intel_encoder *encoder,

			const struct intel_crtc_state *config);

void intel_disable_dsi_pll(struct intel_encoder *encoder);

u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,

void vlv_dsi_pll_disable(struct intel_encoder *encoder);

u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,

		     struct intel_crtc_state *config);

void intel_dsi_reset_clocks(struct intel_encoder *encoder,

			    enum port port);

void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port);



bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv);

int bxt_dsi_pll_compute(struct intel_encoder *encoder,

			struct intel_crtc_state *config);

void bxt_dsi_pll_enable(struct intel_encoder *encoder,

			const struct intel_crtc_state *config);

void bxt_dsi_pll_disable(struct intel_encoder *encoder);

u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,

		     struct intel_crtc_state *config);

void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port);



/* intel_dsi_vbt.c */

bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id);

drivers/gpu/drm/i915/intel_dsi_vbt.c

+1 −1
Original line number Diff line number Diff line
@@ -181,7 +181,7 @@ static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, 
		break;

	}



	wait_for_dsi_fifo_empty(intel_dsi, port);

	vlv_dsi_wait_for_fifo_empty(intel_dsi, port);



out:

	data += len;

drivers/gpu/drm/i915/vlv_dsi.c

+39 −22
Original line number Diff line number Diff line
@@ -69,7 +69,7 @@ enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) 
	}

}



void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)

void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)

{

	struct drm_encoder *encoder = &intel_dsi->base.base;

	struct drm_device *dev = encoder->dev;
@@ -342,11 +342,15 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder, 
			pipe_config->cpu_transcoder = TRANSCODER_DSI_C;

		else

			pipe_config->cpu_transcoder = TRANSCODER_DSI_A;

	}



	ret = intel_compute_dsi_pll(encoder, pipe_config);

		ret = bxt_dsi_pll_compute(encoder, pipe_config);

		if (ret)

			return false;

	} else {

		ret = vlv_dsi_pll_compute(encoder, pipe_config);

		if (ret)

			return false;

	}



	pipe_config->clock_set = true;
@@ -810,8 +814,13 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, 
	 * The BIOS may leave the PLL in a wonky state where it doesn't

	 * lock. It needs to be fully powered down to fix it.

	 */

	intel_disable_dsi_pll(encoder);

	intel_enable_dsi_pll(encoder, pipe_config);

	if (IS_GEN9_LP(dev_priv)) {

		bxt_dsi_pll_disable(encoder);

		bxt_dsi_pll_enable(encoder, pipe_config);

	} else {

		vlv_dsi_pll_disable(encoder);

		vlv_dsi_pll_enable(encoder, pipe_config);

	}



	if (IS_BROXTON(dev_priv)) {

		/* Add MIPI IO reset programming for modeset */
@@ -949,7 +958,7 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder, 


	if (is_vid_mode(intel_dsi)) {

		for_each_dsi_port(port, intel_dsi->ports)

			wait_for_dsi_fifo_empty(intel_dsi, port);

			vlv_dsi_wait_for_fifo_empty(intel_dsi, port);



		intel_dsi_port_disable(encoder);

		usleep_range(2000, 5000);
@@ -979,11 +988,13 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder, 
				val & ~MIPIO_RST_CTRL);

	}



	intel_disable_dsi_pll(encoder);



	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {

	if (IS_GEN9_LP(dev_priv)) {

		bxt_dsi_pll_disable(encoder);

	} else {

		u32 val;



		vlv_dsi_pll_disable(encoder);



		val = I915_READ(DSPCLK_GATE_D);

		val &= ~DPOUNIT_CLOCK_GATE_DISABLE;

		I915_WRITE(DSPCLK_GATE_D, val);
@@ -1024,7 +1035,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, 
	 * configuration, otherwise accessing DSI registers will hang the

	 * machine. See BSpec North Display Engine registers/MIPI[BXT].

	 */

	if (IS_GEN9_LP(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))

	if (IS_GEN9_LP(dev_priv) && !bxt_dsi_pll_is_enabled(dev_priv))

		goto out_put_power;



	/* XXX: this only works for one DSI output */
@@ -1247,17 +1258,20 @@ static void intel_dsi_get_config(struct intel_encoder *encoder, 


	pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);



	if (IS_GEN9_LP(dev_priv))

	if (IS_GEN9_LP(dev_priv)) {

		bxt_dsi_get_pipe_config(encoder, pipe_config);



	pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,

		pclk = bxt_dsi_get_pclk(encoder, pipe_config->pipe_bpp,

					pipe_config);

	if (!pclk)

		return;

	} else {

		pclk = vlv_dsi_get_pclk(encoder, pipe_config->pipe_bpp,

					pipe_config);

	}



	if (pclk) {

		pipe_config->base.adjusted_mode.crtc_clock = pclk;

		pipe_config->port_clock = pclk;

	}

}



static enum drm_mode_status

intel_dsi_mode_valid(struct drm_connector *connector,
@@ -1590,7 +1604,10 @@ static void intel_dsi_unprepare(struct intel_encoder *encoder) 
			/* Panel commands can be sent when clock is in LP11 */

			I915_WRITE(MIPI_DEVICE_READY(port), 0x0);



			intel_dsi_reset_clocks(encoder, port);

			if (IS_GEN9_LP(dev_priv))

				bxt_dsi_reset_clocks(encoder, port);

			else

				vlv_dsi_reset_clocks(encoder, port);

			I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);



			val = I915_READ(MIPI_DSI_FUNC_PRG(port));
@@ -1713,7 +1730,7 @@ static void intel_dsi_add_properties(struct intel_connector *connector) 
	}

}



void intel_dsi_init(struct drm_i915_private *dev_priv)

void vlv_dsi_init(struct drm_i915_private *dev_priv)

{

	struct drm_device *dev = &dev_priv->drm;

	struct intel_dsi *intel_dsi;

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