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The codec supports only power-of-two BCLK/LRCK divisors. If either the slot width or the number of slots is not a power of two, the LRCK divisor must be rounded up to provide enough space. To do that, use order_base_2 (instead of ilog2, which rounds down). Since the rounded divisor is also needed for setting the SYSCLK/BCLK divisor, return the order base 2 instead of fully calculating the hardware register encoding. Acked-by:Maxime Ripard <mripard@kernel.org> Signed-off-by:
Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20201014061941.4306-6-samuel@sholland.org Signed-off-by:
Mark Brown <broonie@kernel.org>
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