Commit e4f6b39e authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: remove *_mc_access from display funcs 



These are no longer needed now that we use the fb_location
programmed by the vbios.

Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b3fba8ad

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+0 −3
Original line number Diff line number Diff line
@@ -613,7 +613,6 @@ struct amdgpu_mc { 
	struct amdgpu_irq_src	vm_fault;

	uint32_t		vram_type;

	uint32_t                srbm_soft_reset;

	struct amdgpu_mode_mc_save save;

	bool			prt_warning;

	uint64_t		stolen_size;

	/* apertures */
@@ -1910,8 +1909,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 
#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))

#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))

#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))

#define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))

#define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))

#define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib),  (s), (d), (b))

#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))

#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+0 −6
Original line number Diff line number Diff line
@@ -2851,12 +2851,6 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev) 
		r = amdgpu_suspend(adev);



retry:

		/* Disable fb access */

		if (adev->mode_info.num_crtc) {

			struct amdgpu_mode_mc_save save;

			amdgpu_display_stop_mc_access(adev, &save);

			amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC);

		}

		if (adev->is_atom_fw)

			amdgpu_atomfirmware_scratch_regs_save(adev);

		else

drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h

+0 −10
Original line number Diff line number Diff line
@@ -257,12 +257,6 @@ struct amdgpu_audio { 
	int num_pins;

};



struct amdgpu_mode_mc_save {

	u32 vga_render_control;

	u32 vga_hdp_control;

	bool crtc_enabled[AMDGPU_MAX_CRTCS];

};



struct amdgpu_display_funcs {

	/* display watermarks */

	void (*bandwidth_update)(struct amdgpu_device *adev);
@@ -298,10 +292,6 @@ struct amdgpu_display_funcs { 
			      uint16_t connector_object_id,

			      struct amdgpu_hpd *hpd,

			      struct amdgpu_router *router);

	void (*stop_mc_access)(struct amdgpu_device *adev,

			       struct amdgpu_mode_mc_save *save);

	void (*resume_mc_access)(struct amdgpu_device *adev,

				 struct amdgpu_mode_mc_save *save);

};



struct amdgpu_mode_info {

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

+0 −130
Original line number Diff line number Diff line
@@ -484,134 +484,6 @@ static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev) 
	return true;

}



static void dce_v10_0_stop_mc_access(struct amdgpu_device *adev,

				     struct amdgpu_mode_mc_save *save)

{

	u32 crtc_enabled, tmp;

	int i;



	save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);

	save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);



	/* disable VGA render */

	tmp = RREG32(mmVGA_RENDER_CONTROL);

	tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);

	WREG32(mmVGA_RENDER_CONTROL, tmp);



	/* blank the display controllers */

	for (i = 0; i < adev->mode_info.num_crtc; i++) {

		crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),

					     CRTC_CONTROL, CRTC_MASTER_EN);

		if (crtc_enabled) {

#if 0

			u32 frame_count;

			int j;



			save->crtc_enabled[i] = true;

			tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);

			if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {

				amdgpu_display_vblank_wait(adev, i);

				WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);

				tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);

				WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);

				WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);

			}

			/* wait for the next frame */

			frame_count = amdgpu_display_vblank_get_counter(adev, i);

			for (j = 0; j < adev->usec_timeout; j++) {

				if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)

					break;

				udelay(1);

			}

			tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);

			if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {

				tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);

				WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);

			}

			tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);

			if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {

				tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);

				WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);

			}

#else

			/* XXX this is a hack to avoid strange behavior with EFI on certain systems */

			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);

			tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);

			tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);

			WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);

			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);

			save->crtc_enabled[i] = false;

			/* ***** */

#endif

		} else {

			save->crtc_enabled[i] = false;

		}

	}

}



static void dce_v10_0_resume_mc_access(struct amdgpu_device *adev,

				       struct amdgpu_mode_mc_save *save)

{

	u32 tmp, frame_count;

	int i, j;



	/* update crtc base addresses */

	for (i = 0; i < adev->mode_info.num_crtc; i++) {

		WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],

		       upper_32_bits(adev->mc.vram_start));

		WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],

		       upper_32_bits(adev->mc.vram_start));

		WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],

		       (u32)adev->mc.vram_start);

		WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],

		       (u32)adev->mc.vram_start);



		if (save->crtc_enabled[i]) {

			tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);

			if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 0) {

				tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 0);

				WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);

			}

			tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);

			if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {

				tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);

				WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);

			}

			tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);

			if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {

				tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);

				WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);

			}

			for (j = 0; j < adev->usec_timeout; j++) {

				tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);

				if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)

					break;

				udelay(1);

			}

			tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);

			tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);

			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);

			WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);

			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);

			/* wait for the next frame */

			frame_count = amdgpu_display_vblank_get_counter(adev, i);

			for (j = 0; j < adev->usec_timeout; j++) {

				if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)

					break;

				udelay(1);

			}

		}

	}



	WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));

	WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));



	/* Unlock vga access */

	WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);

	mdelay(1);

	WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);

}



static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,

					   bool render)

{
@@ -3751,8 +3623,6 @@ static const struct amdgpu_display_funcs dce_v10_0_display_funcs = { 
	.page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos,

	.add_encoder = &dce_v10_0_encoder_add,

	.add_connector = &amdgpu_connector_add,

	.stop_mc_access = &dce_v10_0_stop_mc_access,

	.resume_mc_access = &dce_v10_0_resume_mc_access,

};



static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)

drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

+0 −75
Original line number Diff line number Diff line
@@ -499,79 +499,6 @@ static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev) 
	return true;

}



static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev,

				     struct amdgpu_mode_mc_save *save)

{

	u32 crtc_enabled, tmp;

	int i;



	save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);

	save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);



	/* disable VGA render */

	tmp = RREG32(mmVGA_RENDER_CONTROL);

	tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);

	WREG32(mmVGA_RENDER_CONTROL, tmp);



	/* blank the display controllers */

	for (i = 0; i < adev->mode_info.num_crtc; i++) {

		crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),

					     CRTC_CONTROL, CRTC_MASTER_EN);

		if (crtc_enabled) {

#if 1

			save->crtc_enabled[i] = true;

			tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);

			if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {

				/*it is correct only for RGB ; black is 0*/

				WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0);

				tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);

				WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);

			}

#else

			/* XXX this is a hack to avoid strange behavior with EFI on certain systems */

			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);

			tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);

			tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);

			WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);

			WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);

			save->crtc_enabled[i] = false;

			/* ***** */

#endif

		} else {

			save->crtc_enabled[i] = false;

		}

	}

}



static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev,

				       struct amdgpu_mode_mc_save *save)

{

	u32 tmp;

	int i;



	/* update crtc base addresses */

	for (i = 0; i < adev->mode_info.num_crtc; i++) {

		WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],

		       upper_32_bits(adev->mc.vram_start));

		WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],

		       (u32)adev->mc.vram_start);



		if (save->crtc_enabled[i]) {

			tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);

			tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);

			WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);

		}

	}



	WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));

	WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));



	/* Unlock vga access */

	WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);

	mdelay(1);

	WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);

}



static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,

					   bool render)

{
@@ -3820,8 +3747,6 @@ static const struct amdgpu_display_funcs dce_v11_0_display_funcs = { 
	.page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,

	.add_encoder = &dce_v11_0_encoder_add,

	.add_connector = &amdgpu_connector_add,

	.stop_mc_access = &dce_v11_0_stop_mc_access,

	.resume_mc_access = &dce_v11_0_resume_mc_access,

};



static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)

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