Commit e4deec63 authored by Tejun Heo's avatar Tejun Heo Committed by Jeff Garzik
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[PATCH] sil: apply M15W quirk selectively (take 2) 



 As SII reports that only original 3112's are affected by M15W quirk,
This patch adds SIL_FLAG_MOD15WRITE to selectively apply M15W quirk
depending on chipsets.  As of yet, we don't know exactly which PCI IDs
are for original 3112, so M15W quirk is applied to all except for 3512
and 3124.  Once more info is avaliable, we can change some of these
sil_3112_m15w's to sil_3112.

Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
Signed-off-by: default avatarJeff Garzik <jgarzik@pobox.com>
parent 40e8c82c

drivers/scsi/sata_sil.c

+20 −7
Original line number Diff line number Diff line
@@ -41,8 +41,11 @@ 
#define DRV_VERSION	"0.9"



enum {

	SIL_FLAG_MOD15WRITE	= (1 << 30),



	sil_3112		= 0,

	sil_3114		= 1,

	sil_3112_m15w		= 1,

	sil_3114		= 2,



	SIL_FIFO_R0		= 0x40,

	SIL_FIFO_W0		= 0x41,
@@ -76,13 +79,13 @@ static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); 
static void sil_post_set_mode (struct ata_port *ap);



static struct pci_device_id sil_pci_tbl[] = {

	{ 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },

	{ 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },

	{ 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },

	{ 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },

	{ 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },

	{ 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 },

	{ 0x1002, 0x436e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },

	{ 0x1002, 0x4379, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },

	{ 0x1002, 0x437a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },

	{ 0x1002, 0x436e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },

	{ 0x1002, 0x4379, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },

	{ 0x1002, 0x437a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_m15w },

	{ }	/* terminate list */

};
@@ -174,6 +177,16 @@ static struct ata_port_info sil_port_info[] = { 
		.mwdma_mask	= 0x07,			/* mwdma0-2 */

		.udma_mask	= 0x3f,			/* udma0-5 */

		.port_ops	= &sil_ops,

	}, /* sil_3112_15w - keep it sync'd w/ sil_3112 */

	{

		.sht		= &sil_sht,

		.host_flags	= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |

				  ATA_FLAG_SRST | ATA_FLAG_MMIO |

				  SIL_FLAG_MOD15WRITE,

		.pio_mask	= 0x1f,			/* pio0-4 */

		.mwdma_mask	= 0x07,			/* mwdma0-2 */

		.udma_mask	= 0x3f,			/* udma0-5 */

		.port_ops	= &sil_ops,

	}, /* sil_3114 */

	{

		.sht		= &sil_sht,
@@ -331,7 +344,7 @@ static void sil_dev_config(struct ata_port *ap, struct ata_device *dev) 
		}



	/* limit requests to 15 sectors */

	if (quirks & SIL_QUIRK_MOD15WRITE) {

	if ((ap->flags & SIL_FLAG_MOD15WRITE) && (quirks & SIL_QUIRK_MOD15WRITE)) {

		printk(KERN_INFO "ata%u(%u): applying Seagate errata fix\n",

		       ap->id, dev->devno);

		ap->host->max_sectors = 15;

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