drm/msm/dpu: add support for color processing blocks in dpu driver (e47616df) · Commits · 戴 / test

drivers/gpu/drm/msm/Makefile

+1 −0

Original line number	Diff line number	Diff line
		@@ -65,6 +65,7 @@ msm-y := \
		disp/dpu1/dpu_hw_lm.o \
		disp/dpu1/dpu_hw_pingpong.o \
		disp/dpu1/dpu_hw_sspp.o \
		disp/dpu1/dpu_hw_dspp.o \
		disp/dpu1/dpu_hw_top.o \
		disp/dpu1/dpu_hw_util.o \
		disp/dpu1/dpu_hw_vbif.o \

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -73,12 +73,14 @@ struct dpu_crtc_smmu_state_data {
		* struct dpu_crtc_mixer: stores the map for each virtual pipeline in the CRTC
		* @hw_lm: LM HW Driver context
		* @lm_ctl: CTL Path HW driver context
		* @lm_dspp: DSPP HW driver context
		* @mixer_op_mode: mixer blending operation mode
		* @flush_mask: mixer flush mask for ctl, mixer and pipe
		*/
		struct dpu_crtc_mixer {
		struct dpu_hw_mixer *hw_lm;
		struct dpu_hw_ctl *lm_ctl;
		struct dpu_hw_dspp *hw_dspp;
		u32 mixer_op_mode;
		u32 flush_mask;
		};

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

+11 −1

Original line number	Diff line number	Diff line
		@@ -20,6 +20,7 @@
		#include "dpu_hw_catalog.h"
		#include "dpu_hw_intf.h"
		#include "dpu_hw_ctl.h"
		#include "dpu_hw_dspp.h"
		#include "dpu_formats.h"
		#include "dpu_encoder_phys.h"
		#include "dpu_crtc.h"
		@@ -536,6 +537,7 @@ static struct msm_display_topology dpu_encoder_get_topology(
		* 1 LM, 1 INTF
		* 2 LM, 1 INTF (stream merge to support high resolution interfaces)
		*
		* Adding color blocks only to primary interface
		*/
		if (intf_count == 2)
		topology.num_lm = 2;
		@@ -544,6 +546,9 @@ static struct msm_display_topology dpu_encoder_get_topology(
		else
		topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;

		if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI)
		topology.num_dspp = topology.num_lm;

		topology.num_enc = 0;
		topology.num_intf = intf_count;

		@@ -959,7 +964,8 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
		struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC];
		struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
		struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
		int num_lm, num_ctl, num_pp;
		struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL };
		int num_lm, num_ctl, num_pp, num_dspp;
		int i, j;

		if (!drm_enc) {
		@@ -1008,6 +1014,9 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
		drm_enc->base.id, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl));
		num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
		drm_enc->base.id, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm));
		num_dspp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
		drm_enc->base.id, DPU_HW_BLK_DSPP, hw_dspp,
		ARRAY_SIZE(hw_dspp));

		for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
		dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
		@@ -1020,6 +1029,7 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,

		cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]);
		cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]);
		cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]);
		}

		cstate->num_mixers = num_lm;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c

+29 −10

Original line number	Diff line number	Diff line
		@@ -41,6 +41,8 @@
		#define PINGPONG_SDM845_SPLIT_MASK \
		(PINGPONG_SDM845_MASK \| BIT(DPU_PINGPONG_TE2))

		#define DSPP_SC7180_MASK 0

		#define DEFAULT_PIXEL_RAM_SIZE (50 * 1024)
		#define DEFAULT_DPU_LINE_WIDTH 2048
		#define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560
		@@ -291,29 +293,30 @@ static const struct dpu_lm_sub_blks sdm845_lm_sblk = {
		},
		};

		#define LM_BLK(_name, _id, _base, _fmask, _sblk, _pp, _lmpair) \
		#define LM_BLK(_name, _id, _base, _fmask, _sblk, _pp, _lmpair, _dspp) \
		{ \
		.name = _name, .id = _id, \
		.base = _base, .len = 0x320, \
		.features = _fmask, \
		.sblk = _sblk, \
		.pingpong = _pp, \
		.lm_pair_mask = (1 << _lmpair) \
		.lm_pair_mask = (1 << _lmpair), \
		.dspp = _dspp \
		}

		static const struct dpu_lm_cfg sdm845_lm[] = {
		LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
		&sdm845_lm_sblk, PINGPONG_0, LM_1),
		&sdm845_lm_sblk, PINGPONG_0, LM_1, 0),
		LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
		&sdm845_lm_sblk, PINGPONG_1, LM_0),
		&sdm845_lm_sblk, PINGPONG_1, LM_0, 0),
		LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
		&sdm845_lm_sblk, PINGPONG_2, LM_5),
		&sdm845_lm_sblk, PINGPONG_2, LM_5, 0),
		LM_BLK("lm_3", LM_3, 0x0, MIXER_SDM845_MASK,
		&sdm845_lm_sblk, PINGPONG_MAX, 0),
		&sdm845_lm_sblk, PINGPONG_MAX, 0, 0),
		LM_BLK("lm_4", LM_4, 0x0, MIXER_SDM845_MASK,
		&sdm845_lm_sblk, PINGPONG_MAX, 0),
		&sdm845_lm_sblk, PINGPONG_MAX, 0, 0),
		LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
		&sdm845_lm_sblk, PINGPONG_3, LM_2),
		&sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
		};

		/* SC7180 */
		@@ -328,11 +331,25 @@ static const struct dpu_lm_sub_blks sc7180_lm_sblk = {

		static const struct dpu_lm_cfg sc7180_lm[] = {
		LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK,
		&sc7180_lm_sblk, PINGPONG_0, LM_1),
		&sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
		LM_BLK("lm_1", LM_1, 0x45000, MIXER_SC7180_MASK,
		&sc7180_lm_sblk, PINGPONG_1, LM_0),
		&sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
		};

		/*************************************************************
		* DSPP sub blocks config
		*************************************************************/
		#define DSPP_BLK(_name, _id, _base) \
		{\
		.name = _name, .id = _id, \
		.base = _base, .len = 0x1800, \
		.features = DSPP_SC7180_MASK, \
		.sblk = NULL, \
		}

		static const struct dpu_dspp_cfg sc7180_dspp[] = {
		DSPP_BLK("dspp_0", DSPP_0, 0x54000),
		};
		/*************************************************************
		* PINGPONG sub blocks config
		*************************************************************/
		@@ -587,6 +604,8 @@ static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
		.sspp = sc7180_sspp,
		.mixer_count = ARRAY_SIZE(sc7180_lm),
		.mixer = sc7180_lm,
		.dspp_count = ARRAY_SIZE(sc7180_dspp),
		.dspp = sc7180_dspp,
		.pingpong_count = ARRAY_SIZE(sc7180_pp),
		.pingpong = sc7180_pp,
		.intf_count = ARRAY_SIZE(sc7180_intf),

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h

+39 −0

Original line number	Diff line number	Diff line
		@@ -145,6 +145,17 @@ enum {
		DPU_MIXER_MAX
		};

		/**
		* DSPP sub-blocks
		* @DPU_DSPP_PCC Panel color correction block
		* @DPU_DSPP_GC Gamma correction block
		*/
		enum {
		DPU_DSPP_PCC = 0x1,
		DPU_DSPP_GC,
		DPU_DSPP_MAX
		};

		/**
		* PINGPONG sub-blocks
		* @DPU_PINGPONG_TE Tear check block
		@@ -377,6 +388,16 @@ struct dpu_lm_sub_blks {
		struct dpu_pp_blk gc;
		};

		/**
		* struct dpu_dspp_sub_blks: Information of DSPP block
		* @gc : gamma correction block
		* @pcc: pixel color correction block
		*/
		struct dpu_dspp_sub_blks {
		struct dpu_pp_blk gc;
		struct dpu_pp_blk pcc;
		};

		struct dpu_pingpong_sub_blks {
		struct dpu_pp_blk te;
		struct dpu_pp_blk te2;
		@@ -471,9 +492,23 @@ struct dpu_lm_cfg {
		DPU_HW_BLK_INFO;
		const struct dpu_lm_sub_blks *sblk;
		u32 pingpong;
		u32 dspp;
		unsigned long lm_pair_mask;
		};

		/**
		* struct dpu_dspp_cfg - information of DSPP blocks
		* @id enum identifying this block
		* @base register offset of this block
		* @features bit mask identifying sub-blocks/features
		* supported by this block
		* @sblk sub-blocks information
		*/
		struct dpu_dspp_cfg {
		DPU_HW_BLK_INFO;
		const struct dpu_dspp_sub_blks *sblk;
		};

		/**
		* struct dpu_pingpong_cfg - information of PING-PONG blocks
		* @id enum identifying this block
		@@ -688,6 +723,9 @@ struct dpu_mdss_cfg {

		u32 ad_count;

		u32 dspp_count;
		const struct dpu_dspp_cfg *dspp;

		/* Add additional block data structures here */

		struct dpu_perf_cfg perf;
		@@ -716,6 +754,7 @@ struct dpu_mdss_hw_cfg_handler {
		#define BLK_PINGPONG(s) ((s)->pingpong)
		#define BLK_INTF(s) ((s)->intf)
		#define BLK_AD(s) ((s)->ad)
		#define BLK_DSPP(s) ((s)->dspp)

		/**
		* dpu_hw_catalog_init - dpu hardware catalog init API retrieves

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