Commit e454ff8e authored by Takashi Iwai's avatar Takashi Iwai
Browse files

ALSA: hda/intel: Drop superfluous AZX_DCAPS_I915_POWERWELL checks 



snd_hdac_display_power() can be called even for a HDA controller
without DRM binding.  The same is true for other helpers,
snd_hdac_i915_set_bclk() and snd_hdac_set_codec_wakeup().
So all superfluous AZX_DCAPS_I915_POWERWELL  checks in hda_intel.c can
be dropped, and the definition of AZX_DCAPS_I915_POWERWELL itself can
be removed as well.  This simplifies the code a lot.

Signed-off-by: default avatarTakashi Iwai <tiwai@suse.de>
parent 029d92c2

sound/pci/hda/hda_controller.h

+1 −5
Original line number Diff line number Diff line
@@ -50,11 +50,7 @@ 
/* 24 unused */

#define AZX_DCAPS_COUNT_LPIB_DELAY  (1 << 25)	/* Take LPIB as delay */

#define AZX_DCAPS_PM_RUNTIME	(1 << 26)	/* runtime PM support */

#ifdef CONFIG_SND_HDA_I915

#define AZX_DCAPS_I915_POWERWELL (1 << 27)	/* HSW i915 powerwell support */

#else

#define AZX_DCAPS_I915_POWERWELL 0		/* NOP */

#endif

/* 27 unused */

#define AZX_DCAPS_CORBRP_SELF_CLEAR (1 << 28)	/* CORBRP clears itself after reset */

#define AZX_DCAPS_NO_MSI64      (1 << 29)	/* Stick to 32-bit MSIs */

#define AZX_DCAPS_SEPARATE_STREAM_TAG	(1 << 30) /* capture and playback use separate stream tag */

sound/pci/hda/hda_intel.c

+27 −46
Original line number Diff line number Diff line
@@ -310,31 +310,28 @@ enum { 
#define AZX_DCAPS_INTEL_HASWELL \

	(/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\

	 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\

	 AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))

	 AZX_DCAPS_SNOOP_TYPE(SCH))



/* Broadwell HDMI can't use position buffer reliably, force to use LPIB */

#define AZX_DCAPS_INTEL_BROADWELL \

	(/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\

	 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\

	 AZX_DCAPS_I915_POWERWELL | AZX_DCAPS_SNOOP_TYPE(SCH))

	 AZX_DCAPS_SNOOP_TYPE(SCH))



#define AZX_DCAPS_INTEL_BAYTRAIL \

	(AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT |\

	 AZX_DCAPS_I915_POWERWELL)

	(AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT)



#define AZX_DCAPS_INTEL_BRASWELL \

	(AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\

	 AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL)

	 AZX_DCAPS_I915_COMPONENT)



#define AZX_DCAPS_INTEL_SKYLAKE \

	(AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\

	 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\

	 AZX_DCAPS_I915_POWERWELL)

	 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)



#define AZX_DCAPS_INTEL_BROXTON \

	(AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\

	 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT |\

	 AZX_DCAPS_I915_POWERWELL)

	 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT)



/* quirks for ATI SB / AMD Hudson */

#define AZX_DCAPS_PRESET_ATI_SB \
@@ -591,7 +588,6 @@ static void hda_intel_init_chip(struct azx *chip, bool full_reset) 
	struct pci_dev *pci = chip->pci;

	u32 val;



	if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)

	snd_hdac_set_codec_wakeup(bus, true);

	if (chip->driver_type == AZX_DRIVER_SKL) {

		pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
@@ -604,7 +600,7 @@ static void hda_intel_init_chip(struct azx *chip, bool full_reset) 
		val = val | INTEL_HDA_CGCTL_MISCBDCGE;

		pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);

	}

	if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)



	snd_hdac_set_codec_wakeup(bus, false);



	/* reduce dma latency to avoid noise */
@@ -945,13 +941,9 @@ static bool azx_is_pm_ready(struct snd_card *card) 


static void __azx_runtime_suspend(struct azx *chip)

{

	struct hda_intel *hda = container_of(chip, struct hda_intel, chip);



	azx_stop_chip(chip);

	azx_enter_link_reset(chip);

	azx_clear_irq_pending(chip);

	if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&

	    hda->need_i915_power)

	display_power(chip, false);

}
@@ -962,11 +954,9 @@ static void __azx_runtime_resume(struct azx *chip) 
	struct hda_codec *codec;

	int status;



	if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {

	display_power(chip, true);

	if (hda->need_i915_power)

		snd_hdac_i915_set_bclk(bus);

	}



	/* Read STATESTS before controller reset */

	status = azx_readw(chip, STATESTS);
@@ -982,8 +972,7 @@ static void __azx_runtime_resume(struct azx *chip) 
	}



	/* power down again for link-controlled chips */

	if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&

	    !hda->need_i915_power)

	if (!hda->need_i915_power)

		display_power(chip, false);

}
@@ -1347,11 +1336,8 @@ static int azx_free(struct azx *chip) 
#ifdef CONFIG_SND_HDA_PATCH_LOADER

	release_firmware(chip->fw);

#endif



	if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {

		if (hda->need_i915_power)

	display_power(chip, false);

	}



	if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT)

		snd_hdac_i915_exit(bus);

	kfree(hda);
@@ -1908,7 +1894,6 @@ static int azx_first_init(struct azx *chip) 
	/* initialize chip */

	azx_init_pci(chip);



	if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)

	snd_hdac_i915_set_bclk(bus);



	hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
@@ -2217,10 +2202,13 @@ static int azx_probe_continue(struct azx *chip) 
				goto out_free;

			} else {

				/* don't bother any longer */

				chip->driver_caps &=

					~(AZX_DCAPS_I915_COMPONENT | AZX_DCAPS_I915_POWERWELL);

				chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT;

			}

		}



		/* HSW/BDW controllers need this power */

		if (CONTROLLER_IN_GPU(pci))

			hda->need_i915_power = 1;

	}



	/* Request display power well for the HDA controller or codec. For
@@ -2228,18 +2216,12 @@ static int azx_probe_continue(struct azx *chip) 
	 * this power. For other platforms, like Baytrail/Braswell, only the

	 * display codec needs the power and it can be released after probe.

	 */

	if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {

		/* HSW/BDW controllers need this power */

		if (CONTROLLER_IN_GPU(pci))

			hda->need_i915_power = 1;



	err = display_power(chip, true);

	if (err < 0) {

		dev_err(chip->card->dev,

			"Cannot turn on display power on i915\n");

		goto i915_power_fail;

	}

	}



	err = azx_first_init(chip);

	if (err < 0)
@@ -2287,8 +2269,7 @@ static int azx_probe_continue(struct azx *chip) 
		pm_runtime_put_autosuspend(&pci->dev);



out_free:

	if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL)

		&& !hda->need_i915_power)

	if (!hda->need_i915_power)

		display_power(chip, false);



i915_power_fail:

CRA Git | Maintained and supported by SUSTech CRA and CCSE