Commit e44d62d1 authored by Tvrtko Ursulin's avatar Tvrtko Ursulin
Browse files

drm/i915: Remove POSTING_READ16 



Only a few call sites remain which have been converted to uncore mmio
accessors and so the macro can be removed.

ENGINE_POSTING_READ16 is added to replace one engine->mmio_base relative
call site.

Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190611104548.30545-3-tvrtko.ursulin@linux.intel.com
parent e33a4be8

drivers/gpu/drm/i915/gt/intel_engine.h

+1 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ struct drm_printer; 
#define ENGINE_READ(...)	__ENGINE_READ_OP(read, __VA_ARGS__)

#define ENGINE_READ_FW(...)	__ENGINE_READ_OP(read_fw, __VA_ARGS__)

#define ENGINE_POSTING_READ(...) __ENGINE_READ_OP(posting_read, __VA_ARGS__)

#define ENGINE_POSTING_READ16(...) __ENGINE_READ_OP(posting_read16, __VA_ARGS__)



#define ENGINE_READ64(engine__, lower_reg__, upper_reg__) \

	__ENGINE_REG_OP(read64_2x32, (engine__), \

drivers/gpu/drm/i915/gt/intel_ringbuffer.c

+4 −4
Original line number Diff line number Diff line
@@ -976,11 +976,11 @@ i9xx_irq_disable(struct intel_engine_cs *engine) 
static void

i8xx_irq_enable(struct intel_engine_cs *engine)

{

	struct drm_i915_private *dev_priv = engine->i915;

	struct drm_i915_private *i915 = engine->i915;



	dev_priv->irq_mask &= ~engine->irq_enable_mask;

	I915_WRITE16(GEN2_IMR, dev_priv->irq_mask);

	POSTING_READ16(RING_IMR(engine->mmio_base));

	i915->irq_mask &= ~engine->irq_enable_mask;

	intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask);

	ENGINE_POSTING_READ16(engine, RING_IMR);

}



static void

drivers/gpu/drm/i915/i915_drv.h

+0 −1
Original line number Diff line number Diff line
@@ -2847,7 +2847,6 @@ extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 
#define I915_WRITE_NOTRACE(reg__, val__) __I915_REG_OP(write_notrace, dev_priv, (reg__), (val__))



#define POSTING_READ(reg__)	__I915_REG_OP(posting_read, dev_priv, (reg__))

#define POSTING_READ16(reg__)	__I915_REG_OP(posting_read16, dev_priv, (reg__))



/* These are untraced mmio-accessors that are only valid to be used inside

 * critical sections, such as inside IRQ handlers, where forcewake is explicitly

drivers/gpu/drm/i915/intel_pm.c

+6 −5
Original line number Diff line number Diff line
@@ -6406,13 +6406,14 @@ void intel_init_ipc(struct drm_i915_private *dev_priv) 
 */

DEFINE_SPINLOCK(mchdev_lock);



bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)

bool ironlake_set_drps(struct drm_i915_private *i915, u8 val)

{

	struct intel_uncore *uncore = &i915->uncore;

	u16 rgvswctl;



	lockdep_assert_held(&mchdev_lock);



	rgvswctl = I915_READ16(MEMSWCTL);

	rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);

	if (rgvswctl & MEMCTL_CMD_STS) {

		DRM_DEBUG("gpu busy, RCS change rejected\n");

		return false; /* still busy with another command */
@@ -6420,11 +6421,11 @@ bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val) 


	rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |

		(val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;

	I915_WRITE16(MEMSWCTL, rgvswctl);

	POSTING_READ16(MEMSWCTL);

	intel_uncore_write16(uncore, MEMSWCTL, rgvswctl);

	intel_uncore_posting_read16(uncore, MEMSWCTL);



	rgvswctl |= MEMCTL_CMD_STS;

	I915_WRITE16(MEMSWCTL, rgvswctl);

	intel_uncore_write16(uncore, MEMSWCTL, rgvswctl);



	return true;

}

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