Commit e44c1e3a authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-5.6-2020-02-12' of... 

Merge tag 'amd-drm-fixes-5.6-2020-02-12' of git://people.freedesktop.org/~agd5f/linux

 into drm-fixes

amd-drm-fixes-5.6-2020-02-12:

amdgpu:
- Additional OD fixes for navi
- Misc display fixes
- VCN 2.5 DPG fix
- Prevent build errors on PowerPC on some configs
- GDS EDC fix

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200212224746.3992-1-alexander.deucher@amd.com
parents 7ebdc26a e33a8cfd

drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c

+8 −7
Original line number Diff line number Diff line
@@ -52,7 +52,7 @@ static int amdgpu_perf_event_init(struct perf_event *event) 
		return -ENOENT;



	/* update the hw_perf_event struct with config data */

	hwc->conf = event->attr.config;

	hwc->config = event->attr.config;



	return 0;

}
@@ -74,9 +74,9 @@ static void amdgpu_perf_start(struct perf_event *event, int flags) 
	switch (pe->pmu_perf_type) {

	case PERF_TYPE_AMDGPU_DF:

		if (!(flags & PERF_EF_RELOAD))

			pe->adev->df.funcs->pmc_start(pe->adev, hwc->conf, 1);

			pe->adev->df.funcs->pmc_start(pe->adev, hwc->config, 1);



		pe->adev->df.funcs->pmc_start(pe->adev, hwc->conf, 0);

		pe->adev->df.funcs->pmc_start(pe->adev, hwc->config, 0);

		break;

	default:

		break;
@@ -101,7 +101,7 @@ static void amdgpu_perf_read(struct perf_event *event) 


		switch (pe->pmu_perf_type) {

		case PERF_TYPE_AMDGPU_DF:

			pe->adev->df.funcs->pmc_get_count(pe->adev, hwc->conf,

			pe->adev->df.funcs->pmc_get_count(pe->adev, hwc->config,

							  &count);

			break;

		default:
@@ -126,7 +126,7 @@ static void amdgpu_perf_stop(struct perf_event *event, int flags) 


	switch (pe->pmu_perf_type) {

	case PERF_TYPE_AMDGPU_DF:

		pe->adev->df.funcs->pmc_stop(pe->adev, hwc->conf, 0);

		pe->adev->df.funcs->pmc_stop(pe->adev, hwc->config, 0);

		break;

	default:

		break;
@@ -156,7 +156,8 @@ static int amdgpu_perf_add(struct perf_event *event, int flags) 


	switch (pe->pmu_perf_type) {

	case PERF_TYPE_AMDGPU_DF:

		retval = pe->adev->df.funcs->pmc_start(pe->adev, hwc->conf, 1);

		retval = pe->adev->df.funcs->pmc_start(pe->adev,

						       hwc->config, 1);

		break;

	default:

		return 0;
@@ -184,7 +185,7 @@ static void amdgpu_perf_del(struct perf_event *event, int flags) 


	switch (pe->pmu_perf_type) {

	case PERF_TYPE_AMDGPU_DF:

		pe->adev->df.funcs->pmc_stop(pe->adev, hwc->conf, 1);

		pe->adev->df.funcs->pmc_stop(pe->adev, hwc->config, 1);

		break;

	default:

		break;

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

+1 −2
Original line number Diff line number Diff line
@@ -179,6 +179,7 @@ struct amdgpu_vcn_inst { 
	struct amdgpu_irq_src	irq;

	struct amdgpu_vcn_reg	external;

	struct amdgpu_bo	*dpg_sram_bo;

	struct dpg_pause_state	pause_state;

	void			*dpg_sram_cpu_addr;

	uint64_t		dpg_sram_gpu_addr;

	uint32_t		*dpg_sram_curr_addr;
@@ -190,8 +191,6 @@ struct amdgpu_vcn { 
	const struct firmware	*fw;	/* VCN firmware */

	unsigned		num_enc_rings;

	enum amd_powergating_state cur_state;

	struct dpg_pause_state pause_state;



	bool			indirect_sram;



	uint8_t	num_vcn_inst;

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+11 −3
Original line number Diff line number Diff line
@@ -4374,9 +4374,17 @@ static int gfx_v9_0_ecc_late_init(void *handle) 
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	int r;



	/*

	 * Temp workaround to fix the issue that CP firmware fails to

	 * update read pointer when CPDMA is writing clearing operation

	 * to GDS in suspend/resume sequence on several cards. So just

	 * limit this operation in cold boot sequence.

	 */

	if (!adev->in_suspend) {

		r = gfx_v9_0_do_edc_gds_workarounds(adev);

		if (r)

			return r;

	}



	/* requires IBs so do in late init after IB pool is initialized */

	r = gfx_v9_0_do_edc_gpr_workarounds(adev);

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

+8 −6
Original line number Diff line number Diff line
@@ -1207,9 +1207,10 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 
	struct amdgpu_ring *ring;



	/* pause/unpause if state is changed */

	if (adev->vcn.pause_state.fw_based != new_state->fw_based) {

	if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {

		DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",

			adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg,

			adev->vcn.inst[inst_idx].pause_state.fw_based,

			adev->vcn.inst[inst_idx].pause_state.jpeg,

			new_state->fw_based, new_state->jpeg);



		reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
@@ -1258,13 +1259,14 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 
			reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;

			WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);

		}

		adev->vcn.pause_state.fw_based = new_state->fw_based;

		adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;

	}



	/* pause/unpause if state is changed */

	if (adev->vcn.pause_state.jpeg != new_state->jpeg) {

	if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) {

		DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",

			adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg,

			adev->vcn.inst[inst_idx].pause_state.fw_based,

			adev->vcn.inst[inst_idx].pause_state.jpeg,

			new_state->fw_based, new_state->jpeg);



		reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
@@ -1318,7 +1320,7 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 
			reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;

			WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);

		}

		adev->vcn.pause_state.jpeg = new_state->jpeg;

		adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg;

	}



	return 0;

drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c

+3 −3
Original line number Diff line number Diff line
@@ -1137,9 +1137,9 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev, 
	int ret_code;



	/* pause/unpause if state is changed */

	if (adev->vcn.pause_state.fw_based != new_state->fw_based) {

	if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {

		DRM_DEBUG("dpg pause state changed %d -> %d",

			adev->vcn.pause_state.fw_based,	new_state->fw_based);

			adev->vcn.inst[inst_idx].pause_state.fw_based,	new_state->fw_based);

		reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &

			(~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
@@ -1185,7 +1185,7 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev, 
			reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;

			WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);

		}

		adev->vcn.pause_state.fw_based = new_state->fw_based;

		adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;

	}



	return 0;

CRA Git | Maintained and supported by SUSTech CRA and CCSE