Commit e4494ad6 authored by Martin Blumenstingl's avatar Martin Blumenstingl
Browse files

clk: meson: meson8b: Add the Ethernet (RMII) clock tree on Meson8 



Add the Ethernet clock tree on Meson8 which consists of:
- an input mux - the only known input is the RMII reference clock signal
  which is an input on one of the SoC's pads
- a divider
- 0° or 180° phase change
- a gate to enable/disable the clock

Add these clocks only for Meson8 because they're only known to be used
there.

Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
parent b3506097

drivers/clk/meson/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ config COMMON_CLK_MESON8B 
	default y

	select COMMON_CLK_MESON_REGMAP

	select COMMON_CLK_MESON_MPLL

	select COMMON_CLK_MESON_PHASE

	select COMMON_CLK_MESON_PLL

	select MFD_SYSCON

	select RESET_CONTROLLER

drivers/clk/meson/meson8b.c

+81 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 


#include "meson8b.h"

#include "clk-regmap.h"

#include "clk-phase.h"

#include "clk-pll.h"

#include "clk-mpll.h"
@@ -2663,6 +2664,78 @@ static struct clk_regmap meson8b_cts_i958 = { 
	},

};



static u32 meson8_eth_clk_mux_table[] = { 7 };



static struct clk_regmap meson8_eth_clk_sel = {

	.data = &(struct clk_regmap_mux_data) {

		.offset = HHI_ETH_CLK_CNTL,

		.mask = 0x7,

		.shift = 9,

		.table = meson8_eth_clk_mux_table,

	},

	.hw.init = &(struct clk_init_data) {

		.name = "eth_clk_sel",

		.ops = &clk_regmap_mux_ops,

		.parent_data = &(const struct clk_parent_data) {

			/* TODO: all other parents are unknown */

			.fw_name = "rmii_clk",

		},

		.num_parents = 1,

	},

};



static struct clk_regmap meson8_eth_clk_div = {

	.data = &(struct clk_regmap_div_data) {

		.offset = HHI_ETH_CLK_CNTL,

		.shift = 0,

		.width = 8,

	},

	.hw.init = &(struct clk_init_data) {

		.name = "eth_clk_div",

		.ops = &clk_regmap_divider_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&meson8_eth_clk_sel.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap meson8_eth_clk_phase = {

	.data = &(struct meson_clk_phase_data) {

		.ph = {

			.reg_off = HHI_ETH_CLK_CNTL,

			.shift = 14,

			.width = 1,

		},

	},

	.hw.init = &(struct clk_init_data){

		.name = "eth_clk_inverted",

		.ops = &meson_clk_phase_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&meson8_eth_clk_div.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



static struct clk_regmap meson8_eth_clk_gate = {

	.data = &(struct clk_regmap_gate_data) {

		.offset = HHI_ETH_CLK_CNTL,

		.bit_idx = 8,

	},

	.hw.init = &(struct clk_init_data){

		.name = "eth_clk_en",

		.ops = &clk_regmap_gate_ops,

		.parent_hws = (const struct clk_hw *[]) {

			&meson8_eth_clk_phase.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},

};



#define MESON_GATE(_name, _reg, _bit) \

	MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw)
@@ -2958,6 +3031,10 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = { 
		[CLKID_CTS_MCLK_I958_DIV]   = &meson8b_cts_mclk_i958_div.hw,

		[CLKID_CTS_MCLK_I958]	    = &meson8b_cts_mclk_i958.hw,

		[CLKID_CTS_I958]	    = &meson8b_cts_i958.hw,

		[CLKID_ETH_CLK_SEL]	    = &meson8_eth_clk_sel.hw,

		[CLKID_ETH_CLK_DIV]	    = &meson8_eth_clk_div.hw,

		[CLKID_ETH_CLK_PHASE]	    = &meson8_eth_clk_phase.hw,

		[CLKID_ETH_CLK]		    = &meson8_eth_clk_gate.hw,

		[CLK_NR_CLKS]		    = NULL,

	},

	.num = CLK_NR_CLKS,
@@ -3592,6 +3669,10 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = { 
	&meson8b_cts_mclk_i958_div,

	&meson8b_cts_mclk_i958,

	&meson8b_cts_i958,

	&meson8_eth_clk_sel,

	&meson8_eth_clk_div,

	&meson8_eth_clk_phase,

	&meson8_eth_clk_gate,

};



static const struct meson8b_clk_reset_line {

drivers/clk/meson/meson8b.h

+5 −1
Original line number Diff line number Diff line
@@ -43,6 +43,7 @@ 
#define HHI_MALI_CLK_CNTL		0x1b0 /* 0x6c offset in data sheet */

#define HHI_VPU_CLK_CNTL		0x1bc /* 0x6f offset in data sheet */

#define HHI_HDMI_CLK_CNTL		0x1cc /* 0x73 offset in data sheet */

#define HHI_ETH_CLK_CNTL		0x1d8 /* 0x76 offset in data sheet */

#define HHI_VDEC_CLK_CNTL		0x1e0 /* 0x78 offset in data sheet */

#define HHI_VDEC2_CLK_CNTL		0x1e4 /* 0x79 offset in data sheet */

#define HHI_VDEC3_CLK_CNTL		0x1e8 /* 0x7a offset in data sheet */
@@ -182,8 +183,11 @@ 
#define CLKID_CTS_MCLK_I958_DIV	211

#define CLKID_VCLK_EN		214

#define CLKID_VCLK2_EN		215

#define CLKID_ETH_CLK_SEL	216

#define CLKID_ETH_CLK_DIV	217

#define CLKID_ETH_CLK_PHASE	218



#define CLK_NR_CLKS		216

#define CLK_NR_CLKS		220



/*

 * include the CLKID and RESETID that have

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