Commit e443b333 authored by Alexander Shishkin's avatar Alexander Shishkin Committed by Greg Kroah-Hartman
Browse files

usb: chipidea: split the driver code into units 



Split the driver into the following parts:
  * core  -- resources, register access, capabilities, etc;
  * udc   -- device controller functionality;
  * debug -- logging events.

Signed-off-by: default avatarAlexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent bc25a80d

drivers/usb/chipidea/Kconfig

+18 −2
Original line number Diff line number Diff line 
config USB_CHIPIDEA

	tristate "ChipIdea Highspeed Dual Role Controller"

	depends on USB && USB_GADGET

	select USB_GADGET_DUALSPEED

	depends on USB

	help

          Say Y here if your system has a dual role high speed USB

          controller based on ChipIdea silicon IP. Currently, only the

	  peripheral mode is supported.



	  When compiled dynamically, the module will be called ci-hdrc.ko.



if USB_CHIPIDEA



config USB_CHIPIDEA_UDC

	bool "ChipIdea device controller"

	depends on USB_GADGET

	select USB_GADGET_DUALSPEED

	help

	  Say Y here to enable device controller functionality of the

	  ChipIdea driver.



config USB_CHIPIDEA_DEBUG

	bool "ChipIdea driver debug"

	help

	  Say Y here to enable debugging output of the ChipIdea driver.



endif

drivers/usb/chipidea/Makefile

+3 −1
Original line number Diff line number Diff line 
obj-$(CONFIG_USB_CHIPIDEA)		+= ci_hdrc.o



ci_hdrc-y				:= ci13xxx_udc.o

ci_hdrc-y				:= core.o

ci_hdrc-$(CONFIG_USB_CHIPIDEA_UDC)	+= udc.o

ci_hdrc-$(CONFIG_USB_CHIPIDEA_DEBUG)	+= debug.o



ifneq ($(CONFIG_PCI),)

	obj-$(CONFIG_USB_CHIPIDEA)	+= ci13xxx_pci.o

drivers/usb/chipidea/bits.h

0 → 100644
+71 −0
Original line number Diff line number Diff line 
/*

 * bits.h - register bits of the ChipIdea USB IP core

 *

 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.

 *

 * Author: David Lopo

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */



#ifndef __DRIVERS_USB_CHIPIDEA_BITS_H

#define __DRIVERS_USB_CHIPIDEA_BITS_H



/* HCCPARAMS */

#define HCCPARAMS_LEN         BIT(17)



/* DCCPARAMS */

#define DCCPARAMS_DEN         (0x1F << 0)

#define DCCPARAMS_DC          BIT(7)



/* TESTMODE */

#define TESTMODE_FORCE        BIT(0)



/* USBCMD */

#define USBCMD_RS             BIT(0)

#define USBCMD_RST            BIT(1)

#define USBCMD_SUTW           BIT(13)

#define USBCMD_ATDTW          BIT(14)



/* USBSTS & USBINTR */

#define USBi_UI               BIT(0)

#define USBi_UEI              BIT(1)

#define USBi_PCI              BIT(2)

#define USBi_URI              BIT(6)

#define USBi_SLI              BIT(8)



/* DEVICEADDR */

#define DEVICEADDR_USBADRA    BIT(24)

#define DEVICEADDR_USBADR     (0x7FUL << 25)



/* PORTSC */

#define PORTSC_FPR            BIT(6)

#define PORTSC_SUSP           BIT(7)

#define PORTSC_HSP            BIT(9)

#define PORTSC_PTC            (0x0FUL << 16)



/* DEVLC */

#define DEVLC_PSPD            (0x03UL << 25)

#define    DEVLC_PSPD_HS      (0x02UL << 25)



/* USBMODE */

#define USBMODE_CM            (0x03UL <<  0)

#define    USBMODE_CM_IDLE    (0x00UL <<  0)

#define    USBMODE_CM_DEVICE  (0x02UL <<  0)

#define    USBMODE_CM_HOST    (0x03UL <<  0)

#define USBMODE_SLOM          BIT(3)

#define USBMODE_SDIS          BIT(4)



/* ENDPTCTRL */

#define ENDPTCTRL_RXS         BIT(0)

#define ENDPTCTRL_RXT         (0x03UL <<  2)

#define ENDPTCTRL_RXR         BIT(6)         /* reserved for port 0 */

#define ENDPTCTRL_RXE         BIT(7)

#define ENDPTCTRL_TXS         BIT(16)

#define ENDPTCTRL_TXT         (0x03UL << 18)

#define ENDPTCTRL_TXR         BIT(22)        /* reserved for port 0 */

#define ENDPTCTRL_TXE         BIT(23)



#endif /* __DRIVERS_USB_CHIPIDEA_BITS_H */

drivers/usb/chipidea/ci13xxx_udc.h→drivers/usb/chipidea/ci.h

+204 −0
Original line number Diff line number Diff line 
/*

 * ci13xxx_udc.h - structures, registers, and macros MIPS USB IP core

 * ci.h - common structures, functions, and macros of the ChipIdea driver

 *

 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.

 *
@@ -8,77 +8,24 @@ 
 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * Description: MIPS USB IP core family device controller

 *              Structures, registers and logging macros

 */



#ifndef _CI13XXX_h_

#define _CI13XXX_h_

#ifndef __DRIVERS_USB_CHIPIDEA_CI_H

#define __DRIVERS_USB_CHIPIDEA_CI_H



#include <linux/list.h>

#include <linux/usb/gadget.h>



/******************************************************************************

 * DEFINE

 *****************************************************************************/

#define DMA_ADDR_INVALID	(~(dma_addr_t)0)

#define CI13XXX_PAGE_SIZE  4096ul /* page size for TD's */

#define ENDPT_MAX          32

#define CTRL_PAYLOAD_MAX   64

#define RX        0  /* similar to USB_DIR_OUT but can be used as an index */

#define TX        1  /* similar to USB_DIR_IN  but can be used as an index */



/******************************************************************************

 * STRUCTURES

 *****************************************************************************/

/* DMA layout of transfer descriptors */

struct ci13xxx_td {

	/* 0 */

	u32 next;

#define TD_TERMINATE          BIT(0)

#define TD_ADDR_MASK          (0xFFFFFFEUL << 5)

	/* 1 */

	u32 token;

#define TD_STATUS             (0x00FFUL <<  0)

#define TD_STATUS_TR_ERR      BIT(3)

#define TD_STATUS_DT_ERR      BIT(5)

#define TD_STATUS_HALTED      BIT(6)

#define TD_STATUS_ACTIVE      BIT(7)

#define TD_MULTO              (0x0003UL << 10)

#define TD_IOC                BIT(15)

#define TD_TOTAL_BYTES        (0x7FFFUL << 16)

	/* 2 */

	u32 page[5];

#define TD_CURR_OFFSET        (0x0FFFUL <<  0)

#define TD_FRAME_NUM          (0x07FFUL <<  0)

#define TD_RESERVED_MASK      (0x0FFFUL <<  0)

} __attribute__ ((packed));



/* DMA layout of queue heads */

struct ci13xxx_qh {

	/* 0 */

	u32 cap;

#define QH_IOS                BIT(15)

#define QH_MAX_PKT            (0x07FFUL << 16)

#define QH_ZLT                BIT(29)

#define QH_MULT               (0x0003UL << 30)

	/* 1 */

	u32 curr;

	/* 2 - 8 */

	struct ci13xxx_td        td;

	/* 9 */

	u32 RESERVED;

	struct usb_ctrlrequest   setup;

} __attribute__ ((packed));



/* Extension of usb_request */

struct ci13xxx_req {

	struct usb_request   req;

	unsigned             map;

	struct list_head     queue;

	struct ci13xxx_td   *ptr;

	dma_addr_t           dma;

	struct ci13xxx_td   *zptr;

	dma_addr_t           zdma;

};



/* Extension of usb_ep */

struct ci13xxx_ep {

	struct usb_ep                          ep;
@@ -100,22 +47,6 @@ struct ci13xxx_ep { 
	struct dma_pool                       *td_pool;

};



struct ci13xxx;

struct ci13xxx_udc_driver {

	const char	*name;

	/* offset of the capability registers */

	uintptr_t	 capoffset;

	unsigned long	 flags;

#define CI13XXX_REGS_SHARED		BIT(0)

#define CI13XXX_REQUIRE_TRANSCEIVER	BIT(1)

#define CI13XXX_PULLUP_ON_VBUS		BIT(2)

#define CI13XXX_DISABLE_STREAMING	BIT(3)



#define CI13XXX_CONTROLLER_RESET_EVENT		0

#define CI13XXX_CONTROLLER_STOPPED_EVENT	1

	void	(*notify_event) (struct ci13xxx *udc, unsigned event);

};



struct hw_bank {

	unsigned      lpm;    /* is LPM? */

	void __iomem *abs;    /* bus map offset */
@@ -159,9 +90,6 @@ struct ci13xxx { 
/******************************************************************************

 * REGISTERS

 *****************************************************************************/

/* Default offset of capability registers */

#define DEF_CAPOFFSET		0x100



/* register size */

#define REG_BITS   (32)
@@ -190,59 +118,87 @@ enum ci13xxx_regs { 
	OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,

};



/* HCCPARAMS */

#define HCCPARAMS_LEN         BIT(17)



/* DCCPARAMS */

#define DCCPARAMS_DEN         (0x1F << 0)

#define DCCPARAMS_DC          BIT(7)



/* TESTMODE */

#define TESTMODE_FORCE        BIT(0)



/* USBCMD */

#define USBCMD_RS             BIT(0)

#define USBCMD_RST            BIT(1)

#define USBCMD_SUTW           BIT(13)

#define USBCMD_ATDTW          BIT(14)



/* USBSTS & USBINTR */

#define USBi_UI               BIT(0)

#define USBi_UEI              BIT(1)

#define USBi_PCI              BIT(2)

#define USBi_URI              BIT(6)

#define USBi_SLI              BIT(8)



/* DEVICEADDR */

#define DEVICEADDR_USBADRA    BIT(24)

#define DEVICEADDR_USBADR     (0x7FUL << 25)



/* PORTSC */

#define PORTSC_FPR            BIT(6)

#define PORTSC_SUSP           BIT(7)

#define PORTSC_HSP            BIT(9)

#define PORTSC_PTC            (0x0FUL << 16)



/* DEVLC */

#define DEVLC_PSPD            (0x03UL << 25)

#define    DEVLC_PSPD_HS      (0x02UL << 25)



/* USBMODE */

#define USBMODE_CM            (0x03UL <<  0)

#define    USBMODE_CM_IDLE    (0x00UL <<  0)

#define    USBMODE_CM_DEVICE  (0x02UL <<  0)

#define    USBMODE_CM_HOST    (0x03UL <<  0)

#define USBMODE_SLOM          BIT(3)

#define USBMODE_SDIS          BIT(4)



/* ENDPTCTRL */

#define ENDPTCTRL_RXS         BIT(0)

#define ENDPTCTRL_RXT         (0x03UL <<  2)

#define ENDPTCTRL_RXR         BIT(6)         /* reserved for port 0 */

#define ENDPTCTRL_RXE         BIT(7)

#define ENDPTCTRL_TXS         BIT(16)

#define ENDPTCTRL_TXT         (0x03UL << 18)

#define ENDPTCTRL_TXR         BIT(22)        /* reserved for port 0 */

#define ENDPTCTRL_TXE         BIT(23)



#endif	/* _CI13XXX_h_ */
 


/**

 * ffs_nr: find first (least significant) bit set

 * @x: the word to search

 *

 * This function returns bit number (instead of position)

 */

static inline int ffs_nr(u32 x)

{

	int n = ffs(x);



	return n ? n-1 : 32;

}



/**

 * hw_read: reads from a hw register

 * @reg:  register index

 * @mask: bitfield mask

 *

 * This function returns register contents

 */

static inline u32 hw_read(struct ci13xxx *udc, enum ci13xxx_regs reg, u32 mask)

{

	return ioread32(udc->hw_bank.regmap[reg]) & mask;

}



/**

 * hw_write: writes to a hw register

 * @reg:  register index

 * @mask: bitfield mask

 * @data: new value

 */

static inline void hw_write(struct ci13xxx *udc, enum ci13xxx_regs reg,

			    u32 mask, u32 data)

{

	if (~mask)

		data = (ioread32(udc->hw_bank.regmap[reg]) & ~mask)

			| (data & mask);



	iowrite32(data, udc->hw_bank.regmap[reg]);

}



/**

 * hw_test_and_clear: tests & clears a hw register

 * @reg:  register index

 * @mask: bitfield mask

 *

 * This function returns register contents

 */

static inline u32 hw_test_and_clear(struct ci13xxx *udc, enum ci13xxx_regs reg,

				    u32 mask)

{

	u32 val = ioread32(udc->hw_bank.regmap[reg]) & mask;



	iowrite32(val, udc->hw_bank.regmap[reg]);

	return val;

}



/**

 * hw_test_and_write: tests & writes a hw register

 * @reg:  register index

 * @mask: bitfield mask

 * @data: new value

 *

 * This function returns register contents

 */

static inline u32 hw_test_and_write(struct ci13xxx *udc, enum ci13xxx_regs reg,

				    u32 mask, u32 data)

{

	u32 val = hw_read(udc, reg, ~0);



	hw_write(udc, reg, mask, data);

	return (val & mask) >> ffs_nr(mask);

}



int hw_device_init(struct ci13xxx *udc, void __iomem *base,

		   uintptr_t cap_offset);

int hw_device_reset(struct ci13xxx *ci);



int hw_port_test_set(struct ci13xxx *ci, u8 mode);



u8 hw_port_test_get(struct ci13xxx *ci);



#endif	/* __DRIVERS_USB_CHIPIDEA_CI_H */

drivers/usb/chipidea/ci13xxx_msm.c

+2 −1
Original line number Diff line number Diff line
@@ -11,8 +11,9 @@ 
#include <linux/usb/msm_hsusb_hw.h>

#include <linux/usb/ulpi.h>

#include <linux/usb/gadget.h>

#include <linux/usb/chipidea.h>



#include "ci13xxx_udc.h"

#include "ci.h"



#define MSM_USB_BASE	(udc->regs)

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