Commit e42da8a1 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'renesas-dt2-for-v3.20' of... 

Merge tag 'renesas-dt2-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Merge "Second Round of Renesas ARM Based SoC DT Updates for v3.20" from Simon
Horman:

* Support Renesas memory controllers
* Add SRC interrupt number on r8a779~ and r8a7791 SoCs
* Fix MSTP8 input clocks on r8a7791 SoC
* Add PM domain support to r8a7740
* Add DT bindings for the R-Mobile System Controller
* Use Add sh73a0-specific FSI2 compatible property

* tag 'renesas-dt2-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas

:
  PM / Domains: R-Mobile SYSC: Document SH-Mobile AG5 (sh73a0) binding
  ARM: shmobile: sh73a0 dtsi: Add memory-controller nodes
  ARM: shmobile: r8a7740 dtsi: Add memory-controller node
  ARM: shmobile: r8a73a4 dtsi: Add memory-controller nodes
  ARM: shmobile: Add DT bindings for Renesas memory controllers
  ARM: shmobile: r8a7791: add SRC interrupt number on DTSI
  ARM: shmobile: r8a7790: add SRC interrupt number on DTSI
  ARM: shmobile: r8a7791: fix MSTP8 input clocks
  ARM: shmobile: r8a7740 dtsi: Add PM domain support
  PM / Domains: Add DT bindings for the R-Mobile System Controller
  ARM: shmobile: sh73a0 dtsi: Add SoC-specific FSI2 compatible property

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 6937dbff fbaa5e69

Documentation/devicetree/bindings/memory-controllers/renesas-memory-controllers.txt

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+44 −0
Original line number Diff line number Diff line 
DT bindings for Renesas R-Mobile and SH-Mobile memory controllers

=================================================================



Renesas R-Mobile and SH-Mobile SoCs contain one or more memory controllers.

These memory controllers differ from one SoC variant to another, and are called

by different names ("DDR Bus Controller (DBSC)", "DDR3 Bus State Controller

(DBSC3)", "SDRAM Bus State Controller (SBSC)").



Currently memory controller device nodes are used only to reference PM

domains, and prevent these PM domains from being powered down, which would

crash the system.



As there exist no actual drivers for these controllers yet, these bindings

should be considered EXPERIMENTAL for now.



Required properties:

  - compatible: Must be one of the following SoC-specific values:

		  - "renesas,dbsc-r8a73a4" (R-Mobile APE6)

		  - "renesas,dbsc3-r8a7740" (R-Mobile A1)

		  - "renesas,sbsc-sh73a0" (SH-Mobile AG5)

  - reg: Must contain the base address and length of the memory controller's

	 registers.



Optional properties:

  - interrupts: Must contain a list of interrupt specifiers for memory

		controller interrupts, if available.

  - interrupts-names: Must contain a list of interrupt names corresponding to

		      the interrupts in the interrupts property, if available.

		      Valid interrupt names are:

			- "sec" (secure interrupt)

			- "temp" (normal (temperature) interrupt)

  - power-domains: Must contain a reference to the PM domain that the memory

		   controller belongs to, if available.



Example:



	sbsc1: memory-controller@fe400000 {

		compatible = "renesas,sbsc-sh73a0";

		reg = <0xfe400000 0x400>;

		interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>,

			     <0 36 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "sec", "temp";

		power-domains = <&pd_a4bc0>;

	};

Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt

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+99 −0
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DT bindings for the Renesas R-Mobile System Controller



== System Controller Node ==



The R-Mobile System Controller provides the following functions:

  - Boot mode management,

  - Reset generation,

  - Power management.



Required properties:

- compatible: Should be "renesas,sysc-<soctype>", "renesas,sysc-rmobile" as

	      fallback.

	      Examples with soctypes are:

		- "renesas,sysc-r8a7740" (R-Mobile A1)

		- "renesas,sysc-sh73a0" (SH-Mobile AG5)

- reg: Two address start and address range blocks for the device:

         - The first block refers to the normally accessible registers,

         - the second block refers to the registers protected by the HPB

	   semaphore.



Optional nodes:

- pm-domains: This node contains a hierarchy of PM domain nodes, which should

  match the Power Area Hierarchy in the Power Domain Specifications section of

  the device's datasheet.





== PM Domain Nodes ==



Each of the PM domain nodes represents a PM domain, as documented by the

generic PM domain bindings in

Documentation/devicetree/bindings/power/power_domain.txt.



The nodes should be named by the real power area names, and thus their names

should be unique.



Required properties:

  - #power-domain-cells: Must be 0.



Optional properties:

- reg: If the PM domain is not always-on, this property must contain the bit

       index number for the corresponding power area in the various Power

       Control and Status Registers. The parent's node must contain the

       following two properties:

	 - #address-cells: Must be 1,

	 - #size-cells: Must be 0.

       If the PM domain is always-on, this property must be omitted.





Example:



This shows a subset of the r8a7740 PM domain hierarchy, containing the

C5 "always-on" domain, 2 of its subdomains (A4S and A4SU), and the A3SP domain,

which is a subdomain of A4S.



	sysc: system-controller@e6180000 {

		compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile";

		reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;



		pm-domains {

			pd_c5: c5 {

				#address-cells = <1>;

				#size-cells = <0>;

				#power-domain-cells = <0>;



				pd_a4s: a4s@10 {

					reg = <10>;

					#address-cells = <1>;

					#size-cells = <0>;

					#power-domain-cells = <0>;



					pd_a3sp: a3sp@11 {

						reg = <11>;

						#power-domain-cells = <0>;

					};

				};



				pd_a4su: a4su@20 {

					reg = <20>;

					#power-domain-cells = <0>;

				};

			};

		};

	};





== PM Domain Consumers ==



Hardware blocks belonging to a PM domain should contain a "power-domains"

property that is a phandle pointing to the corresponding PM domain node.



Example:



	tpu: pwm@e6600000 {

		compatible = "renesas,tpu-r8a7740", "renesas,tpu";

		reg = <0xe6600000 0x100>;

		clocks = <&mstp3_clks R8A7740_CLK_TPU0>;

		power-domains = <&pd_a3sp>;

		#pwm-cells = <3>;

	};

arch/arm/boot/dts/r8a73a4.dtsi

+10 −0
Original line number Diff line number Diff line
@@ -38,6 +38,16 @@ 
			     <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

	};



	dbsc1: memory-controller@e6790000 {

		compatible = "renesas,dbsc-r8a73a4";

		reg = <0 0xe6790000 0 0x10000>;

	};



	dbsc2: memory-controller@e67a0000 {

		compatible = "renesas,dbsc-r8a73a4";

		reg = <0 0xe67a0000 0 0x10000>;

	};



	dmac: dma-multiplexer {

		compatible = "renesas,shdma-mux";

		#dma-cells = <1>;

arch/arm/boot/dts/r8a7740.dtsi

+105 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 
			device_type = "cpu";

			reg = <0x0>;

			clock-frequency = <800000000>;

			power-domains = <&pd_a3sm>;

		};

	};
@@ -36,17 +37,29 @@ 
		      <0xc2000000 0x1000>;

	};



	dbsc3: memory-controller@fe400000 {

		compatible = "renesas,dbsc3-r8a7740";

		reg = <0xfe400000 0x400>;

		power-domains = <&pd_a4s>;

	};



	pmu {

		compatible = "arm,cortex-a9-pmu";

		interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;

	};



	ptm {

		compatible = "arm,coresight-etm3x";

		power-domains = <&pd_d4>;

	};



	cmt1: timer@e6138000 {

		compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";

		reg = <0xe6138000 0x170>;

		interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp3_clks R8A7740_CLK_CMT1>;

		clock-names = "fck";

		power-domains = <&pd_c5>;



		renesas,channels-mask = <0x3f>;
@@ -72,6 +85,7 @@ 
			      0 149 IRQ_TYPE_LEVEL_HIGH

			      0 149 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp2_clks R8A7740_CLK_INTCA>;

		power-domains = <&pd_a4s>;

	};



	/* irqpin1: IRQ8 - IRQ15 */
@@ -93,6 +107,7 @@ 
			      0 149 IRQ_TYPE_LEVEL_HIGH

			      0 149 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp2_clks R8A7740_CLK_INTCA>;

		power-domains = <&pd_a4s>;

	};



	/* irqpin2: IRQ16 - IRQ23 */
@@ -114,6 +129,7 @@ 
			      0 149 IRQ_TYPE_LEVEL_HIGH

			      0 149 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp2_clks R8A7740_CLK_INTCA>;

		power-domains = <&pd_a4s>;

	};



	/* irqpin3: IRQ24 - IRQ31 */
@@ -135,6 +151,7 @@ 
			      0 149 IRQ_TYPE_LEVEL_HIGH

			      0 149 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp2_clks R8A7740_CLK_INTCA>;

		power-domains = <&pd_a4s>;

	};



	ether: ethernet@e9a00000 {
@@ -143,6 +160,7 @@ 
		      <0xe9a01800 0x800>;

		interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp3_clks R8A7740_CLK_GETHER>;

		power-domains = <&pd_a4s>;

		phy-mode = "mii";

		#address-cells = <1>;

		#size-cells = <0>;
@@ -159,6 +177,7 @@ 
			      0 203 IRQ_TYPE_LEVEL_HIGH

			      0 204 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp1_clks R8A7740_CLK_IIC0>;

		power-domains = <&pd_a4r>;

		status = "disabled";

	};
@@ -172,6 +191,7 @@ 
			      0 72 IRQ_TYPE_LEVEL_HIGH

			      0 73 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp3_clks R8A7740_CLK_IIC1>;

		power-domains = <&pd_a3sp>;

		status = "disabled";

	};
@@ -181,6 +201,7 @@ 
		interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;

		clock-names = "sci_ick";

		power-domains = <&pd_a3sp>;

		status = "disabled";

	};
@@ -190,6 +211,7 @@ 
		interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;

		clock-names = "sci_ick";

		power-domains = <&pd_a3sp>;

		status = "disabled";

	};
@@ -199,6 +221,7 @@ 
		interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;

		clock-names = "sci_ick";

		power-domains = <&pd_a3sp>;

		status = "disabled";

	};
@@ -208,6 +231,7 @@ 
		interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;

		clock-names = "sci_ick";

		power-domains = <&pd_a3sp>;

		status = "disabled";

	};
@@ -217,6 +241,7 @@ 
		interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;

		clock-names = "sci_ick";

		power-domains = <&pd_a3sp>;

		status = "disabled";

	};
@@ -226,6 +251,7 @@ 
		interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;

		clock-names = "sci_ick";

		power-domains = <&pd_a3sp>;

		status = "disabled";

	};
@@ -235,6 +261,7 @@ 
		interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;

		clock-names = "sci_ick";

		power-domains = <&pd_a3sp>;

		status = "disabled";

	};
@@ -244,6 +271,7 @@ 
		interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;

		clock-names = "sci_ick";

		power-domains = <&pd_a3sp>;

		status = "disabled";

	};
@@ -253,6 +281,7 @@ 
		interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;

		clock-names = "sci_ick";

		power-domains = <&pd_a3sp>;

		status = "disabled";

	};
@@ -271,12 +300,14 @@ 
			<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,

			<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,

			<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;

		power-domains = <&pd_c5>;

	};



	tpu: pwm@e6600000 {

		compatible = "renesas,tpu-r8a7740", "renesas,tpu";

		reg = <0xe6600000 0x100>;

		clocks = <&mstp3_clks R8A7740_CLK_TPU0>;

		power-domains = <&pd_a3sp>;

		status = "disabled";

		#pwm-cells = <3>;

	};
@@ -287,6 +318,7 @@ 
		interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH

			      0 57 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp3_clks R8A7740_CLK_MMC>;

		power-domains = <&pd_a3sp>;

		status = "disabled";

	};
@@ -297,6 +329,7 @@ 
			      0 118 IRQ_TYPE_LEVEL_HIGH

			      0 119 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;

		power-domains = <&pd_a3sp>;

		cap-sd-highspeed;

		cap-sdio-irq;

		status = "disabled";
@@ -309,6 +342,7 @@ 
			      0 122 IRQ_TYPE_LEVEL_HIGH

			      0 123 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;

		power-domains = <&pd_a3sp>;

		cap-sd-highspeed;

		cap-sdio-irq;

		status = "disabled";
@@ -321,6 +355,7 @@ 
			      0 126 IRQ_TYPE_LEVEL_HIGH

			      0 127 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;

		power-domains = <&pd_a3sp>;

		cap-sd-highspeed;

		cap-sdio-irq;

		status = "disabled";
@@ -332,6 +367,7 @@ 
		reg = <0xfe1f0000 0x400>;

		interrupts = <0 9 0x4>;

		clocks = <&mstp3_clks R8A7740_CLK_FSI>;

		power-domains = <&pd_a4mp>;

		status = "disabled";

	};
@@ -343,6 +379,7 @@ 
			     <0 200 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp1_clks R8A7740_CLK_TMU0>;

		clock-names = "fck";

		power-domains = <&pd_a4r>;



		#renesas,channels = <3>;
@@ -357,6 +394,7 @@ 
			     <0 172 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp1_clks R8A7740_CLK_TMU1>;

		clock-names = "fck";

		power-domains = <&pd_a4r>;



		#renesas,channels = <3>;
@@ -543,4 +581,71 @@ 
				"usbhost", "sdhi2", "usbfunc", "usphy";

		};

	};



	sysc: system-controller@e6180000 {

		compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile";

		reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;



		pm-domains {

			pd_c5: c5 {

				#address-cells = <1>;

				#size-cells = <0>;

				#power-domain-cells = <0>;



				pd_a4lc: a4lc@1 {

					reg = <1>;

					#power-domain-cells = <0>;

				};



				pd_a4mp: a4mp@2 {

					reg = <2>;

					#power-domain-cells = <0>;

				};



				pd_d4: d4@3 {

					reg = <3>;

					#power-domain-cells = <0>;

				};



				pd_a4r: a4r@5 {

					reg = <5>;

					#address-cells = <1>;

					#size-cells = <0>;

					#power-domain-cells = <0>;



					pd_a3rv: a3rv@6 {

						reg = <6>;

						#power-domain-cells = <0>;

					};

				};



				pd_a4s: a4s@10 {

					reg = <10>;

					#address-cells = <1>;

					#size-cells = <0>;

					#power-domain-cells = <0>;



					pd_a3sp: a3sp@11 {

						reg = <11>;

						#power-domain-cells = <0>;

					};



					pd_a3sm: a3sm@12 {

						reg = <12>;

						#power-domain-cells = <0>;

					};



					pd_a3sg: a3sg@13 {

						reg = <13>;

						#power-domain-cells = <0>;

					};

				};



				pd_a4su: a4su@20 {

					reg = <20>;

					#power-domain-cells = <0>;

				};

			};

		};

	};

};

arch/arm/boot/dts/r8a7790.dtsi

+10 −10
Original line number Diff line number Diff line
@@ -1440,16 +1440,16 @@ 
		};



		rcar_sound,src {

			src0: src@0 { };

			src1: src@1 { };

			src2: src@2 { };

			src3: src@3 { };

			src4: src@4 { };

			src5: src@5 { };

			src6: src@6 { };

			src7: src@7 { };

			src8: src@8 { };

			src9: src@9 { };

			src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; };

			src1: src@1 { interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; };

			src2: src@2 { interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; };

			src3: src@3 { interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; };

			src4: src@4 { interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; };

			src5: src@5 { interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; };

			src6: src@6 { interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; };

			src7: src@7 { interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; };

			src8: src@8 { interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; };

			src9: src@9 { interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; };

		};



		rcar_sound,ssi {

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