Commit e42c3d85 authored by Ben Hutchings's avatar Ben Hutchings
Browse files

sfc: Refactor queue teardown sequence to allow for EF10 flush behaviour 



Currently efx_stop_datapath() will try to flush our DMA queues (if DMA
is enabled), then finalise software and hardware state for each queue.
However, for EF10 we must ask the MC to finalise each queue, which
implicitly starts flushing it, and then wait for the flush events.
We therefore need to delegate more of this to the NIC type.

Combine all the hardware operations into a new NIC-type operation
efx_nic_type::fini_dmaq, and call this before tearing down the
software state and buffers for all the DMA queues.

Signed-off-by: default avatarBen Hutchings <bhutchings@solarflare.com>
parent 501a248c

drivers/net/ethernet/sfc/efx.c

+19 −21
Original line number Diff line number Diff line
@@ -640,7 +640,6 @@ static void efx_stop_datapath(struct efx_nic *efx) 
	struct efx_channel *channel;

	struct efx_tx_queue *tx_queue;

	struct efx_rx_queue *rx_queue;

	struct pci_dev *dev = efx->pci_dev;

	int rc;



	EFX_ASSERT_RESET_SERIALISED(efx);
@@ -652,15 +651,26 @@ static void efx_stop_datapath(struct efx_nic *efx) 
			rx_queue->refill_enabled = false;

	}



	/* Only perform flush if dma is enabled */

	if (dev->is_busmaster && efx->state != STATE_RECOVERY) {

		rc = efx_nic_flush_queues(efx);

	efx_for_each_channel(channel, efx) {

		/* RX packet processing is pipelined, so wait for the

		 * NAPI handler to complete.  At least event queue 0

		 * might be kept active by non-data events, so don't

		 * use napi_synchronize() but actually disable NAPI

		 * temporarily.

		 */

		if (efx_channel_has_rx_queue(channel)) {

			efx_stop_eventq(channel);

			efx_start_eventq(channel);

		}

	}



	rc = efx->type->fini_dmaq(efx);

	if (rc && EFX_WORKAROUND_7803(efx)) {

		/* Schedule a reset to recover from the flush failure. The

		 * descriptor caches reference memory we're about to free,

		 * but falcon_reconfigure_mac_wrapper() won't reconnect

			 * the MACs because of the pending reset. */

		 * the MACs because of the pending reset.

		 */

		netif_err(efx, drv, efx->net_dev,

			  "Resetting to recover from flush failure\n");

		efx_schedule_reset(efx, RESET_TYPE_ALL);
@@ -670,20 +680,8 @@ static void efx_stop_datapath(struct efx_nic *efx) 
		netif_dbg(efx, drv, efx->net_dev,

			  "successfully flushed all queues\n");

	}

	}



	efx_for_each_channel(channel, efx) {

		/* RX packet processing is pipelined, so wait for the

		 * NAPI handler to complete.  At least event queue 0

		 * might be kept active by non-data events, so don't

		 * use napi_synchronize() but actually disable NAPI

		 * temporarily.

		 */

		if (efx_channel_has_rx_queue(channel)) {

			efx_stop_eventq(channel);

			efx_start_eventq(channel);

		}



		efx_for_each_channel_rx_queue(rx_queue, channel)

			efx_fini_rx_queue(rx_queue);

		efx_for_each_possible_channel_tx_queue(tx_queue, channel)

drivers/net/ethernet/sfc/efx.h

+0 −1
Original line number Diff line number Diff line
@@ -23,7 +23,6 @@ extern void efx_remove_tx_queue(struct efx_tx_queue *tx_queue); 
extern void efx_init_tx_queue(struct efx_tx_queue *tx_queue);

extern void efx_init_tx_queue_core_txq(struct efx_tx_queue *tx_queue);

extern void efx_fini_tx_queue(struct efx_tx_queue *tx_queue);

extern void efx_release_tx_buffers(struct efx_tx_queue *tx_queue);

extern netdev_tx_t

efx_hard_start_xmit(struct sk_buff *skb, struct net_device *net_dev);

extern netdev_tx_t

drivers/net/ethernet/sfc/falcon.c

+2 −0
Original line number Diff line number Diff line
@@ -2351,6 +2351,7 @@ const struct efx_nic_type falcon_a1_nic_type = { 
	.probe_port = falcon_probe_port,

	.remove_port = falcon_remove_port,

	.handle_global_event = falcon_handle_global_event,

	.fini_dmaq = efx_farch_fini_dmaq,

	.prepare_flush = falcon_prepare_flush,

	.finish_flush = efx_port_dummy_op_void,

	.update_stats = falcon_update_nic_stats,
@@ -2396,6 +2397,7 @@ const struct efx_nic_type falcon_b0_nic_type = { 
	.probe_port = falcon_probe_port,

	.remove_port = falcon_remove_port,

	.handle_global_event = falcon_handle_global_event,

	.fini_dmaq = efx_farch_fini_dmaq,

	.prepare_flush = falcon_prepare_flush,

	.finish_flush = efx_port_dummy_op_void,

	.update_stats = falcon_update_nic_stats,

drivers/net/ethernet/sfc/net_driver.h

+5 −1
Original line number Diff line number Diff line
@@ -953,8 +953,11 @@ static inline unsigned int efx_port_num(struct efx_nic *efx) 
 * @probe_port: Probe the MAC and PHY

 * @remove_port: Free resources allocated by probe_port()

 * @handle_global_event: Handle a "global" event (may be %NULL)

 * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues)

 * @prepare_flush: Prepare the hardware for flushing the DMA queues

 * @finish_flush: Clean up after flushing the DMA queues

 *	(for Falcon architecture)

 * @finish_flush: Clean up after flushing the DMA queues (for Falcon

 *	architecture)

 * @update_stats: Update statistics not provided by event handling

 * @start_stats: Start the regular fetching of statistics

 * @stop_stats: Stop the regular fetching of statistics
@@ -1014,6 +1017,7 @@ struct efx_nic_type { 
	int (*probe_port)(struct efx_nic *efx);

	void (*remove_port)(struct efx_nic *efx);

	bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *);

	int (*fini_dmaq)(struct efx_nic *efx);

	void (*prepare_flush)(struct efx_nic *efx);

	void (*finish_flush)(struct efx_nic *efx);

	void (*update_stats)(struct efx_nic *efx);

drivers/net/ethernet/sfc/nic.c

+27 −4
Original line number Diff line number Diff line
@@ -721,7 +721,7 @@ static bool efx_check_tx_flush_complete(struct efx_nic *efx) 
/* Flush all the transmit queues, and continue flushing receive queues until

 * they're all flushed. Wait for the DRAIN events to be recieved so that there

 * are no more RX and TX events left on any channel. */

int efx_nic_flush_queues(struct efx_nic *efx)

static int efx_farch_do_flush(struct efx_nic *efx)

{

	unsigned timeout = msecs_to_jiffies(5000); /* 5s for all flushes and drains */

	struct efx_channel *channel;
@@ -729,8 +729,6 @@ int efx_nic_flush_queues(struct efx_nic *efx) 
	struct efx_tx_queue *tx_queue;

	int rc = 0;



	efx->type->prepare_flush(efx);



	efx_for_each_channel(channel, efx) {

		efx_for_each_channel_tx_queue(tx_queue, channel) {

			atomic_inc(&efx->drain_pending);
@@ -791,7 +789,32 @@ int efx_nic_flush_queues(struct efx_nic *efx) 
		atomic_set(&efx->rxq_flush_outstanding, 0);

	}



	return rc;

}



int efx_farch_fini_dmaq(struct efx_nic *efx)

{

	struct efx_channel *channel;

	struct efx_tx_queue *tx_queue;

	struct efx_rx_queue *rx_queue;

	int rc = 0;



	/* Do not attempt to write to the NIC during EEH recovery */

	if (efx->state != STATE_RECOVERY) {

		/* Only perform flush if DMA is enabled */

		if (efx->pci_dev->is_busmaster) {

			efx->type->prepare_flush(efx);

			rc = efx_farch_do_flush(efx);

			efx->type->finish_flush(efx);

		}



		efx_for_each_channel(channel, efx) {

			efx_for_each_channel_rx_queue(rx_queue, channel)

				efx_nic_fini_rx(rx_queue);

			efx_for_each_channel_tx_queue(tx_queue, channel)

				efx_nic_fini_tx(tx_queue);

		}

	}



	return rc;

}

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