Commit e426ab39 authored Aug 14, 2020 by Christophe Leroy Committed by Michael Ellerman Sep 02, 2020

powerpc: Remove flush_instruction_cache for book3s/32

The only callers of flush_instruction_cache() are:

arch/powerpc/kernel/swsusp_booke.S: bl flush_instruction_cache
arch/powerpc/mm/nohash/40x.c: flush_instruction_cache();
arch/powerpc/mm/nohash/44x.c: flush_instruction_cache();
arch/powerpc/mm/nohash/fsl_booke.c: flush_instruction_cache();
arch/powerpc/platforms/44x/machine_check.c: flush_instruction_cache();
arch/powerpc/platforms/44x/machine_check.c: flush_instruction_cache();

This function is not used by book3s/32, drop it.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/50098f49877cea0f46730a9df82dcabf84160e4b.1597384512.git.christophe.leroy@csgroup.eu

parent 9d6792ff

arch/powerpc/kernel/misc_32.S

+2 −10

Original line number	Diff line number	Diff line
		@@ -258,9 +258,8 @@ _ASM_NOKPROBE_SYMBOL(real_writeb)

		/*
		* Flush instruction cache.
		* This is a no-op on the 601.
		*/
		#ifndef CONFIG_PPC_8xx
		#if !defined(CONFIG_PPC_8xx) && !defined(CONFIG_PPC_BOOK3S_32)
		_GLOBAL(flush_instruction_cache)
		#if defined(CONFIG_4xx)
		lis r3, KERNELBASE@h
		@@ -277,18 +276,11 @@ _GLOBAL(flush_instruction_cache)
		mfspr r3,SPRN_L1CSR1
		ori r3,r3,L1CSR1_ICFI\|L1CSR1_ICLFR
		mtspr SPRN_L1CSR1,r3
		#elif defined(CONFIG_PPC_BOOK3S_601)
		blr /* for 601, do nothing */
		#else
		/* 603/604 processor - use invalidate-all bit in HID0 */
		mfspr r3,SPRN_HID0
		ori r3,r3,HID0_ICFI
		mtspr SPRN_HID0,r3
		#endif /* CONFIG_4xx */
		isync
		blr
		EXPORT_SYMBOL(flush_instruction_cache)
		#endif /* CONFIG_PPC_8xx */
		#endif

		/*
		* Copy a whole page. We use the dcbz instruction on the destination