Commit e4227bff authored May 12, 2020 by Martin Blumenstingl Committed by David S. Miller May 13, 2020

net: stmmac: dwmac-meson8b: Fetch the "timing-adjustment" clock

The PRG_ETHERNET registers have a built-in timing adjustment circuit
which can provide the RX delay in RGMII mode. This is driven by an
external (to this IP, but internal to the SoC) clock input. Fetch this
clock as optional (even though it's there on all supported SoCs) since
we just learned about it and existing .dtbs don't specify it.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

parent c92d1d23

drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c

+8 −0

Original line number	Diff line number	Diff line
		@@ -85,6 +85,7 @@ struct meson8b_dwmac {
		phy_interface_t phy_mode;
		struct clk *rgmii_tx_clk;
		u32 tx_delay_ns;
		struct clk *timing_adj_clk;
		};

		struct meson8b_dwmac_clk_configs {
		@@ -380,6 +381,13 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)
		&dwmac->tx_delay_ns))
		dwmac->tx_delay_ns = 2;

		dwmac->timing_adj_clk = devm_clk_get_optional(dwmac->dev,
		"timing-adjustment");
		if (IS_ERR(dwmac->timing_adj_clk)) {
		ret = PTR_ERR(dwmac->timing_adj_clk);
		goto err_remove_config_dt;
		}

		ret = meson8b_init_rgmii_tx_clk(dwmac);
		if (ret)
		goto err_remove_config_dt;

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