Commit e420249d authored by Nicholas Piggin's avatar Nicholas Piggin Committed by Michael Ellerman
Browse files

powerpc/64s: Idle do not hold reservation longer than required 



When taking the core idle state lock, grab it immediately like a regular
lock, rather than adding more tests in there. Holding the lock keeps it
stable, so there is no need to do it whole holding the reservation.

Reviewed-by: default avatarGautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent adbcf8d7

arch/powerpc/kernel/idle_book3s.S

+11 −9
Original line number Diff line number Diff line
@@ -556,12 +556,12 @@ BEGIN_FTR_SECTION 
	CHECK_HMI_INTERRUPT

END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)



	lbz	r7,PACA_THREAD_MASK(r13)

	ld	r14,PACA_CORE_IDLE_STATE_PTR(r13)

lwarx_loop2:

	lwarx	r15,0,r14

	andis.	r9,r15,PNV_CORE_IDLE_LOCK_BIT@h

	lbz	r7,PACA_THREAD_MASK(r13)



	/*

	 * Take the core lock to synchronize against other threads.

	 *

	 * Lock bit is set in one of the 2 cases-

	 * a. In the sleep/winkle enter path, the last thread is executing

	 * fastsleep workaround code.
@@ -569,7 +569,14 @@ lwarx_loop2: 
	 * workaround undo code or resyncing timebase or restoring context

	 * In either case loop until the lock bit is cleared.

	 */

1:

	lwarx	r15,0,r14

	andis.	r9,r15,PNV_CORE_IDLE_LOCK_BIT@h

	bnel-	core_idle_lock_held

	oris	r15,r15,PNV_CORE_IDLE_LOCK_BIT@h

	stwcx.	r15,0,r14

	bne-	1b

	isync



	andi.	r9,r15,PNV_CORE_IDLE_THREAD_BITS

	cmpwi	cr2,r9,0
@@ -581,11 +588,6 @@ lwarx_loop2: 
	 * cr4 - gt or eq if waking up from complete hypervisor state loss.

	 */



	oris	r15,r15,PNV_CORE_IDLE_LOCK_BIT@h

	stwcx.	r15,0,r14

	bne-	lwarx_loop2

	isync



BEGIN_FTR_SECTION

	lbz	r4,PACA_SUBCORE_SIBLING_MASK(r13)

	and	r4,r4,r15

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