Commit e4156ee5 authored by Paul Walmsley's avatar Paul Walmsley
Browse files

OMAP4: CM instances: add clockdomain register offsets 



In OMAP4 CM instances, some registers (CM_CLKSTCTRL, CM_STATICDEP,
CM_DYNAMICDEP, and the module-specific registers underneath) are
organized by clockdomain.  Add the clockdomain offset macros to the
appropriate PRCM module header files.

This data was almost completely autogenerated from the TI hardware
database; the autogeneration scripts have been updated.

Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Tested-by: default avatarRajendra Nayak <rnayak@ti.com>
Tested-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
parent b170fbe1

arch/arm/mach-omap2/cm1_44xx.h

+5 −0
Original line number Diff line number Diff line
@@ -40,6 +40,11 @@ 
#define OMAP4430_CM1_RESTORE_INST	0x0e00

#define OMAP4430_CM1_INSTR_INST		0x0f00



/* CM1 clockdomain register offsets (from instance start) */

#define OMAP4430_CM1_ABE_ABE_CDOFFS		0x0000

#define OMAP4430_CM1_MPU_MPU_CDOFFS		0x0000

#define OMAP4430_CM1_TESLA_TESLA_CDOFFS		0x0000



/* CM1 */



/* CM1.OCP_SOCKET_CM1 register offsets */

arch/arm/mach-omap2/cm2_44xx.h

+19 −0
Original line number Diff line number Diff line
@@ -46,6 +46,25 @@ 
#define OMAP4430_CM2_RESTORE_INST	0x1e00

#define OMAP4430_CM2_INSTR_INST		0x1f00



/* CM2 clockdomain register offsets (from instance start) */

#define OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS	0x0000

#define OMAP4430_CM2_CORE_L3_1_CDOFFS		0x0000

#define OMAP4430_CM2_CORE_L3_2_CDOFFS		0x0100

#define OMAP4430_CM2_CORE_DUCATI_CDOFFS		0x0200

#define OMAP4430_CM2_CORE_SDMA_CDOFFS		0x0300

#define OMAP4430_CM2_CORE_MEMIF_CDOFFS		0x0400

#define OMAP4430_CM2_CORE_D2D_CDOFFS		0x0500

#define OMAP4430_CM2_CORE_L4CFG_CDOFFS		0x0600

#define OMAP4430_CM2_CORE_L3INSTR_CDOFFS	0x0700

#define OMAP4430_CM2_IVAHD_IVAHD_CDOFFS		0x0000

#define OMAP4430_CM2_CAM_CAM_CDOFFS		0x0000

#define OMAP4430_CM2_DSS_DSS_CDOFFS		0x0000

#define OMAP4430_CM2_GFX_GFX_CDOFFS		0x0000

#define OMAP4430_CM2_L3INIT_L3INIT_CDOFFS	0x0000

#define OMAP4430_CM2_L4PER_L4PER_CDOFFS		0x0000

#define OMAP4430_CM2_L4PER_L4SEC_CDOFFS		0x0180

#define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS	0x0000





/* CM2 */

arch/arm/mach-omap2/prcm_mpu44xx.h

+5 −0
Original line number Diff line number Diff line
@@ -37,6 +37,11 @@ 
#define OMAP4430_PRCM_MPU_CPU0_INST		0x0400

#define OMAP4430_PRCM_MPU_CPU1_INST		0x0800



/* PRCM_MPU clockdomain register offsets (from instance start) */

#define OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS	0x0000

#define OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS	0x0000





/*

 * PRCM_MPU

 *

arch/arm/mach-omap2/prm44xx.h

+15 −0
Original line number Diff line number Diff line
@@ -56,6 +56,21 @@ 
#define OMAP4430_PRM_DEVICE_INST		0x1b00

#define OMAP4430_PRM_INSTR_INST		0x1f00



/* PRM clockdomain register offsets (from instance start) */

#define OMAP4430_PRM_MPU_MPU_CDOFFS		0x0000

#define OMAP4430_PRM_TESLA_TESLA_CDOFFS		0x0000

#define OMAP4430_PRM_ABE_ABE_CDOFFS		0x0000

#define OMAP4430_PRM_CORE_CORE_CDOFFS		0x0000

#define OMAP4430_PRM_IVAHD_IVAHD_CDOFFS		0x0000

#define OMAP4430_PRM_CAM_CAM_CDOFFS		0x0000

#define OMAP4430_PRM_DSS_DSS_CDOFFS		0x0000

#define OMAP4430_PRM_GFX_GFX_CDOFFS		0x0000

#define OMAP4430_PRM_L3INIT_L3INIT_CDOFFS	0x0000

#define OMAP4430_PRM_L4PER_L4PER_CDOFFS		0x0000

#define OMAP4430_PRM_CEFUSE_CEFUSE_CDOFFS	0x0000

#define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS	0x0000

#define OMAP4430_PRM_EMU_EMU_CDOFFS		0x0000

#define OMAP4430_PRM_EMU_CM_EMU_CDOFFS		0x0000



/* OMAP4 specific register offsets */

#define OMAP4_RM_RSTCTRL				0x0000

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