Commit e40917e4 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'ti-k3-dt-for-v5.11' of... 

Merge tag 'ti-k3-dt-for-v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux into arm/dt

Devicetree changes for TI K3 platforms for v5.11 merge window:

- Standardized usage of "disabled" only in board.dts files, #interrupt-cells warning fixups, node format error fixes

- J721E: R5F support, MMC/SD UHS mode added

- AM654: R5F support, dss marked coherent, drop unused dma-ring-reset-quirk property

- J7200: ADC support, Mailbox, hwspinlock

* tag 'ti-k3-dt-for-v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux: (25 commits)
  arm64: dts: ti: k3-j721e-common-proc-board: Add support for SD card UHS modes
  arm64: dts: ti: k3-j721e-main: Add output tap delay values
  arm64: dts: ti: k3: squelch warning about lack of #interrupt-cells
  arm64: dts: ti: k3-j7200-common-proc-board: Correct the name of io expander on main_i2c1
  arm64: dts: ti: k3-j7200-som-p0: main_i2c0 have an ioexpander on the SOM
  arm64: dts: ti: k3-j7200-som-p0: Add IPC sub-mailbox nodes
  arm64: dts: ti: k3-j7200-main: Add mailbox cluster nodes
  arm64: dts: ti: k3-j7200-main: Add hwspinlock node
  arm64: dts: ti: am65/j721e/j7200: Mark firmware used uart as "reserved"
  arm64: dts: ti: k3-am654-base-board: Fix up un-necessary status set to "okay" for USB
  arm64: dts: ti: am65/j721e: Fix up un-necessary status set to "okay" for crypto
  arm64: dts: ti: k3-j721e*: Cleanup disabled nodes at SoC dtsi level
  arm64: dts: ti: k3-am65*: Cleanup disabled nodes at SoC dtsi level
  arm64: dts: ti: k3-j7200-mcu-wakeup: Enable ADC support
  arm64: dts: ti: k3-am65*/j721e*: Fix unit address format error for dss node
  arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for R5Fs
  arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to R5Fs
  arm64: dts: ti: k3-j721e-main: Add MAIN domain R5F cluster nodes
  arm64: dts: ti: k3-j721e-mcu: Add MCU domain R5F cluster node
  arm64: dts: ti: k3-am654-base-board: Reserve memory for IPC between R5F cores
  ...

Link: https://lore.kernel.org/r/20201130174258.ljsiokkyr7x7tsbd@covenant


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents a2f9886a cd48ce86

arch/arm64/boot/dts/ti/k3-am65-main.dtsi

+3 −10
Original line number Diff line number Diff line
@@ -119,7 +119,6 @@ 
		#address-cells = <2>;

		#size-cells = <2>;

		ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;

		status = "okay";



		dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,

				<&main_udmap 0x4001>;
@@ -473,6 +472,7 @@ 
			interrupt-controller;

			interrupt-parent = <&intr_main_navss>;

			msi-controller;

			#interrupt-cells = <0>;

			ti,sci = <&dmsc>;

			ti,sci-dev-id = <179>;

			ti,interrupt-ranges = <0 0 256>;
@@ -612,7 +612,6 @@ 
			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";

			ti,num-rings = <818>;

			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */

			ti,dma-ring-reset-quirk;

			ti,sci = <&dmsc>;

			ti,sci-dev-id = <187>;

			msi-parent = <&inta_main_udmass>;
@@ -770,8 +769,6 @@ 
		clocks = <&k3_clks 104 0>;

		clock-names = "fck";

		power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;



		status = "disabled";

	};



	mcasp1: mcasp@2b10000 {
@@ -789,8 +786,6 @@ 
		clocks = <&k3_clks 105 0>;

		clock-names = "fck";

		power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;



		status = "disabled";

	};



	mcasp2: mcasp@2b20000 {
@@ -808,8 +803,6 @@ 
		clocks = <&k3_clks 106 0>;

		clock-names = "fck";

		power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;



		status = "disabled";

	};



	cal: cal@6f03000 {
@@ -834,7 +827,7 @@ 
		};

	};



	dss: dss@04a00000 {

	dss: dss@4a00000 {

		compatible = "ti,am65x-dss";

		reg =	<0x0 0x04a00000 0x0 0x1000>, /* common */

			<0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
@@ -865,7 +858,7 @@ 


		interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;



		status = "disabled";

		dma-coherent;



		dss_ports: ports {

			#address-cells = <1>;

arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi

+41 −2
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
/*

 * Device Tree Source for AM6 SoC Family MCU Domain peripherals

 *

 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/

 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/

 */



&cbass_mcu {
@@ -135,7 +135,6 @@ 
			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";

			ti,num-rings = <286>;

			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */

			ti,dma-ring-reset-quirk;

			ti,sci = <&dmsc>;

			ti,sci-dev-id = <195>;

			msi-parent = <&inta_main_udmass>;
@@ -269,4 +268,44 @@ 
			};

		};

	};



	mcu_r5fss0: r5fss@41000000 {

		compatible = "ti,am654-r5fss";

		ti,cluster-mode = <1>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x41000000 0x00 0x41000000 0x20000>,

			 <0x41400000 0x00 0x41400000 0x20000>;

		power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;



		mcu_r5fss0_core0: r5f@41000000 {

			compatible = "ti,am654-r5f";

			reg = <0x41000000 0x00008000>,

			      <0x41010000 0x00008000>;

			reg-names = "atcm", "btcm";

			ti,sci = <&dmsc>;

			ti,sci-dev-id = <159>;

			ti,sci-proc-ids = <0x01 0xff>;

			resets = <&k3_reset 159 1>;

			firmware-name = "am65x-mcu-r5f0_0-fw";

			ti,atcm-enable = <1>;

			ti,btcm-enable = <1>;

			ti,loczrama = <1>;

		};



		mcu_r5fss0_core1: r5f@41400000 {

			compatible = "ti,am654-r5f";

			reg = <0x41400000 0x00008000>,

			      <0x41410000 0x00008000>;

			reg-names = "atcm", "btcm";

			ti,sci = <&dmsc>;

			ti,sci-dev-id = <245>;

			ti,sci-proc-ids = <0x02 0xff>;

			resets = <&k3_reset 245 1>;

			firmware-name = "am65x-mcu-r5f0_1-fw";

			ti,atcm-enable = <1>;

			ti,btcm-enable = <1>;

			ti,loczrama = <1>;

		};

	};

};

arch/arm64/boot/dts/ti/k3-am654-base-board.dts

+61 −10
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/

 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/

 */



/dts-v1/;
@@ -29,11 +29,42 @@ 
		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		secure_ddr: secure-ddr@9e800000 {

			reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */

			alignment = <0x1000>;

			no-map;

		};



		mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {

			compatible = "shared-dma-pool";

			reg = <0 0xa0000000 0 0x100000>;

			no-map;

		};



		mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {

			compatible = "shared-dma-pool";

			reg = <0 0xa0100000 0 0xf00000>;

			no-map;

		};



		mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {

			compatible = "shared-dma-pool";

			reg = <0 0xa1000000 0 0x100000>;

			no-map;

		};



		mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {

			compatible = "shared-dma-pool";

			reg = <0 0xa1100000 0 0xf00000>;

			no-map;

		};



		rtos_ipc_memory_region: ipc-memories@a2000000 {

			reg = <0x00 0xa2000000 0x00 0x00100000>;

			alignment = <0x1000>;

			no-map;

		};

	};



	gpio-keys {
@@ -211,7 +242,7 @@ 


&wkup_uart0 {

	/* Wakeup UART is used by System firmware */

	status = "disabled";

	status = "reserved";

};



&main_uart0 {
@@ -325,14 +356,6 @@ 
	disable-wp;

};



&dwc3_1 {

	status = "okay";

};



&usb1_phy {

	status = "okay";

};



&usb1 {

	pinctrl-names = "default";

	pinctrl-0 = <&usb1_pins_default>;
@@ -441,6 +464,18 @@ 
	status = "disabled";

};



&mcu_r5fss0_core0 {

	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,

			<&mcu_r5fss0_core0_memory_region>;

	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;

};



&mcu_r5fss0_core1 {

	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,

			<&mcu_r5fss0_core1_memory_region>;

	mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;

};



&ospi0 {

	pinctrl-names = "default";

	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
@@ -486,3 +521,19 @@ 
	phy-mode = "rgmii-rxid";

	phy-handle = <&phy0>;

};



&mcasp0 {

	status = "disabled";

};



&mcasp1 {

	status = "disabled";

};



&mcasp2 {

	status = "disabled";

};



&dss {

	status = "disabled";

};

arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts

+19 −14
Original line number Diff line number Diff line
@@ -43,13 +43,6 @@ 
};



&main_pmx0 {

	main_i2c0_pins_default: main-i2c0-pins-default {

		pinctrl-single,pins = <

			J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */

			J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */

		>;

	};



	main_i2c1_pins_default: main-i2c1-pins-default {

		pinctrl-single,pins = <

			J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
@@ -79,7 +72,7 @@ 


&wkup_uart0 {

	/* Wakeup UART is used by System firmware */

	status = "disabled";

	status = "reserved";

};



&main_uart0 {
@@ -89,7 +82,7 @@ 


&main_uart2 {

	/* MAIN UART 2 is used by R5F firmware */

	status = "disabled";

	status = "reserved";

};



&main_uart3 {
@@ -146,10 +139,6 @@ 
};



&main_i2c0 {

	pinctrl-names = "default";

	pinctrl-0 = <&main_i2c0_pins_default>;

	clock-frequency = <400000>;



	exp1: gpio@20 {

		compatible = "ti,tca6416";

		reg = <0x20>;
@@ -165,16 +154,26 @@ 
	};

};



/*

 * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be

 * swapped on the CPB.

 *

 * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3.

 * The i2c1 of the CPB (as it is labeled) is not connected to j7200.

 */

&main_i2c1 {

	pinctrl-names = "default";

	pinctrl-0 = <&main_i2c1_pins_default>;

	clock-frequency = <400000>;



	exp4: gpio@20 {

	exp3: gpio@20 {

		compatible = "ti,tca6408";

		reg = <0x20>;

		gpio-controller;

		#gpio-cells = <2>;

		gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",

				  "UB926_LOCK", "UB926_PWR_SW_CNTRL",

				  "UB926_TUNER_RESET", "UB926_GPIO_SPARE", "";

	};

};
@@ -213,3 +212,9 @@ 
	dr_mode = "otg";

	maximum-speed = "high-speed";

};



&tscadc0 {

	adc {

		ti,adc-channels = <0 1 2 3 4 5 6 7>;

	};

};

arch/arm64/boot/dts/ti/k3-j7200-main.dtsi

+114 −0
Original line number Diff line number Diff line
@@ -115,6 +115,120 @@ 
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;

		};



		hwspinlock: spinlock@30e00000 {

			compatible = "ti,am654-hwspinlock";

			reg = <0x00 0x30e00000 0x00 0x1000>;

			#hwlock-cells = <1>;

		};



		mailbox0_cluster0: mailbox@31f80000 {

			compatible = "ti,am654-mailbox";

			reg = <0x00 0x31f80000 0x00 0x200>;

			#mbox-cells = <1>;

			ti,mbox-num-users = <4>;

			ti,mbox-num-fifos = <16>;

			interrupt-parent = <&main_navss_intr>;

		};



		mailbox0_cluster1: mailbox@31f81000 {

			compatible = "ti,am654-mailbox";

			reg = <0x00 0x31f81000 0x00 0x200>;

			#mbox-cells = <1>;

			ti,mbox-num-users = <4>;

			ti,mbox-num-fifos = <16>;

			interrupt-parent = <&main_navss_intr>;

		};



		mailbox0_cluster2: mailbox@31f82000 {

			compatible = "ti,am654-mailbox";

			reg = <0x00 0x31f82000 0x00 0x200>;

			#mbox-cells = <1>;

			ti,mbox-num-users = <4>;

			ti,mbox-num-fifos = <16>;

			interrupt-parent = <&main_navss_intr>;

		};



		mailbox0_cluster3: mailbox@31f83000 {

			compatible = "ti,am654-mailbox";

			reg = <0x00 0x31f83000 0x00 0x200>;

			#mbox-cells = <1>;

			ti,mbox-num-users = <4>;

			ti,mbox-num-fifos = <16>;

			interrupt-parent = <&main_navss_intr>;

		};



		mailbox0_cluster4: mailbox@31f84000 {

			compatible = "ti,am654-mailbox";

			reg = <0x00 0x31f84000 0x00 0x200>;

			#mbox-cells = <1>;

			ti,mbox-num-users = <4>;

			ti,mbox-num-fifos = <16>;

			interrupt-parent = <&main_navss_intr>;

		};



		mailbox0_cluster5: mailbox@31f85000 {

			compatible = "ti,am654-mailbox";

			reg = <0x00 0x31f85000 0x00 0x200>;

			#mbox-cells = <1>;

			ti,mbox-num-users = <4>;

			ti,mbox-num-fifos = <16>;

			interrupt-parent = <&main_navss_intr>;

		};



		mailbox0_cluster6: mailbox@31f86000 {

			compatible = "ti,am654-mailbox";

			reg = <0x00 0x31f86000 0x00 0x200>;

			#mbox-cells = <1>;

			ti,mbox-num-users = <4>;

			ti,mbox-num-fifos = <16>;

			interrupt-parent = <&main_navss_intr>;

		};



		mailbox0_cluster7: mailbox@31f87000 {

			compatible = "ti,am654-mailbox";

			reg = <0x00 0x31f87000 0x00 0x200>;

			#mbox-cells = <1>;

			ti,mbox-num-users = <4>;

			ti,mbox-num-fifos = <16>;

			interrupt-parent = <&main_navss_intr>;

		};



		mailbox0_cluster8: mailbox@31f88000 {

			compatible = "ti,am654-mailbox";

			reg = <0x00 0x31f88000 0x00 0x200>;

			#mbox-cells = <1>;

			ti,mbox-num-users = <4>;

			ti,mbox-num-fifos = <16>;

			interrupt-parent = <&main_navss_intr>;

		};



		mailbox0_cluster9: mailbox@31f89000 {

			compatible = "ti,am654-mailbox";

			reg = <0x00 0x31f89000 0x00 0x200>;

			#mbox-cells = <1>;

			ti,mbox-num-users = <4>;

			ti,mbox-num-fifos = <16>;

			interrupt-parent = <&main_navss_intr>;

		};



		mailbox0_cluster10: mailbox@31f8a000 {

			compatible = "ti,am654-mailbox";

			reg = <0x00 0x31f8a000 0x00 0x200>;

			#mbox-cells = <1>;

			ti,mbox-num-users = <4>;

			ti,mbox-num-fifos = <16>;

			interrupt-parent = <&main_navss_intr>;

		};



		mailbox0_cluster11: mailbox@31f8b000 {

			compatible = "ti,am654-mailbox";

			reg = <0x00 0x31f8b000 0x00 0x200>;

			#mbox-cells = <1>;

			ti,mbox-num-users = <4>;

			ti,mbox-num-fifos = <16>;

			interrupt-parent = <&main_navss_intr>;

		};



		main_ringacc: ringacc@3c000000 {

			compatible = "ti,am654-navss-ringacc";

			reg =	<0x00 0x3c000000 0x00 0x400000>,

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