Commit e40803f2 authored by Lorenzo Bianconi's avatar Lorenzo Bianconi Committed by Felix Fietkau
Browse files

mt76x2: move mt76x2_dev in mt76x02_util.h 



Move mt76x2_dev in mt76x02_util.h and rename it in mt76x02_dev
in order to be shared between mt76x2 and mt76x0 driver

Signed-off-by: default avatarLorenzo Bianconi <lorenzo.bianconi@redhat.com>
Signed-off-by: default avatarFelix Fietkau <nbd@nbd.name>
parent 46a74187

drivers/net/wireless/mediatek/mt76/mt76x02_dfs.h

0 → 100644
+140 −0
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2016 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>

 *

 * Permission to use, copy, modify, and/or distribute this software for any

 * purpose with or without fee is hereby granted, provided that the above

 * copyright notice and this permission notice appear in all copies.

 *

 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES

 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF

 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES

 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN

 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF

 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

 */



#ifndef __MT76x02_DFS_H

#define __MT76x02_DFS_H



#include <linux/types.h>

#include <linux/nl80211.h>



#define MT_DFS_GP_INTERVAL		(10 << 4) /* 64 us unit */

#define MT_DFS_NUM_ENGINES		4



/* bbp params */

#define MT_DFS_SYM_ROUND		0

#define MT_DFS_DELTA_DELAY		2

#define MT_DFS_VGA_MASK			0

#define MT_DFS_PWR_GAIN_OFFSET		3

#define MT_DFS_PWR_DOWN_TIME		0xf

#define MT_DFS_RX_PE_MASK		0xff

#define MT_DFS_PKT_END_MASK		0

#define MT_DFS_CH_EN			0xf



/* sw detector params */

#define MT_DFS_EVENT_LOOP		64

#define MT_DFS_SW_TIMEOUT		(HZ / 20)

#define MT_DFS_EVENT_WINDOW		(HZ / 5)

#define MT_DFS_SEQUENCE_WINDOW		(200 * (1 << 20))

#define MT_DFS_EVENT_TIME_MARGIN	2000

#define MT_DFS_PRI_MARGIN		4

#define MT_DFS_SEQUENCE_TH		6



#define MT_DFS_FCC_MAX_PRI		((28570 << 1) + 1000)

#define MT_DFS_FCC_MIN_PRI		(3000 - 2)

#define MT_DFS_JP_MAX_PRI		((80000 << 1) + 1000)

#define MT_DFS_JP_MIN_PRI		(28500 - 2)

#define MT_DFS_ETSI_MAX_PRI		(133333 + 125000 + 117647 + 1000)

#define MT_DFS_ETSI_MIN_PRI		(4500 - 20)



struct mt76x02_radar_specs {

	u8 mode;

	u16 avg_len;

	u16 e_low;

	u16 e_high;

	u16 w_low;

	u16 w_high;

	u16 w_margin;

	u32 t_low;

	u32 t_high;

	u16 t_margin;

	u32 b_low;

	u32 b_high;

	u32 event_expiration;

	u16 pwr_jmp;

};



#define MT_DFS_CHECK_EVENT(x)		((x) != GENMASK(31, 0))

#define MT_DFS_EVENT_ENGINE(x)		(((x) & BIT(31)) ? 2 : 0)

#define MT_DFS_EVENT_TIMESTAMP(x)	((x) & GENMASK(21, 0))

#define MT_DFS_EVENT_WIDTH(x)		((x) & GENMASK(11, 0))

struct mt76x02_dfs_event {

	unsigned long fetch_ts;

	u32 ts;

	u16 width;

	u8 engine;

};



#define MT_DFS_EVENT_BUFLEN		256

struct mt76x02_dfs_event_rb {

	struct mt76x02_dfs_event data[MT_DFS_EVENT_BUFLEN];

	int h_rb, t_rb;

};



struct mt76x02_dfs_sequence {

	struct list_head head;

	u32 first_ts;

	u32 last_ts;

	u32 pri;

	u16 count;

	u8 engine;

};



struct mt76x02_dfs_hw_pulse {

	u8 engine;

	u32 period;

	u32 w1;

	u32 w2;

	u32 burst;

};



struct mt76x02_dfs_sw_detector_params {

	u32 min_pri;

	u32 max_pri;

	u32 pri_margin;

};



struct mt76x02_dfs_engine_stats {

	u32 hw_pattern;

	u32 hw_pulse_discarded;

	u32 sw_pattern;

};



struct mt76x02_dfs_seq_stats {

	u32 seq_pool_len;

	u32 seq_len;

};



struct mt76x02_dfs_pattern_detector {

	enum nl80211_dfs_regions region;



	u8 chirp_pulse_cnt;

	u32 chirp_pulse_ts;



	struct mt76x02_dfs_sw_detector_params sw_dpd_params;

	struct mt76x02_dfs_event_rb event_rb[2];



	struct list_head sequences;

	struct list_head seq_pool;

	struct mt76x02_dfs_seq_stats seq_stats;



	unsigned long last_sw_check;

	u32 last_event_ts;



	struct mt76x02_dfs_engine_stats stats[MT_DFS_NUM_ENGINES];

	struct tasklet_struct dfs_tasklet;

};



#endif /* __MT76x02_DFS_H */

drivers/net/wireless/mediatek/mt76/mt76x02_util.h

+69 −0
Original line number Diff line number Diff line
@@ -18,7 +18,76 @@ 
#ifndef __MT76X02_UTIL_H

#define __MT76X02_UTIL_H



#include <linux/kfifo.h>



#include "mt76x02_mac.h"

#include "mt76x02_dfs.h"



#define MT_MAX_CHAINS		2

struct mt76x02_rx_freq_cal {

	s8 high_gain[MT_MAX_CHAINS];

	s8 rssi_offset[MT_MAX_CHAINS];

	s8 lna_gain;

	u32 mcu_gain;

};



struct mt76x02_calibration {

	struct mt76x02_rx_freq_cal rx;



	u8 agc_gain_init[MT_MAX_CHAINS];

	u8 agc_gain_cur[MT_MAX_CHAINS];



	u16 false_cca;

	s8 avg_rssi_all;

	s8 agc_gain_adjust;

	s8 low_gain;



	u8 temp;



	bool init_cal_done;

	bool tssi_cal_done;

	bool tssi_comp_pending;

	bool dpd_cal_done;

	bool channel_cal_done;

};



struct mt76x02_dev {

	struct mt76_dev mt76; /* must be first */



	struct mac_address macaddr_list[8];



	struct mutex mutex;



	u8 txdone_seq;

	DECLARE_KFIFO_PTR(txstatus_fifo, struct mt76x02_tx_status);



	struct sk_buff *rx_head;



	struct tasklet_struct tx_tasklet;

	struct tasklet_struct pre_tbtt_tasklet;

	struct delayed_work cal_work;

	struct delayed_work mac_work;



	u32 aggr_stats[32];



	struct sk_buff *beacons[8];

	u8 beacon_mask;

	u8 beacon_data_mask;



	u8 tbtt_count;

	u16 beacon_int;



	struct mt76x02_calibration cal;



	s8 target_power;

	s8 target_power_delta[2];

	bool enable_tpc;



	u8 coverage_class;

	u8 slottime;



	struct mt76x02_dfs_pattern_detector dfs_pd;

};



extern struct ieee80211_rate mt76x02_rates[12];

drivers/net/wireless/mediatek/mt76/mt76x2/common.c

+1 −1
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ 
void mt76x2_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,

			 struct sk_buff *skb)

{

	struct mt76x2_dev *dev = container_of(mdev, struct mt76x2_dev, mt76);

	struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);

	void *rxwi = skb->data;



	if (q == MT_RXQ_MCU) {

drivers/net/wireless/mediatek/mt76/mt76x2/debugfs.c

+6 −6
Original line number Diff line number Diff line
@@ -20,7 +20,7 @@ 
static int

mt76x2_ampdu_stat_read(struct seq_file *file, void *data)

{

	struct mt76x2_dev *dev = file->private;

	struct mt76x02_dev *dev = file->private;

	int i, j;



	for (i = 0; i < 4; i++) {
@@ -49,7 +49,7 @@ mt76x2_ampdu_stat_open(struct inode *inode, struct file *f) 


static int read_txpower(struct seq_file *file, void *data)

{

	struct mt76x2_dev *dev = dev_get_drvdata(file->private);

	struct mt76x02_dev *dev = dev_get_drvdata(file->private);



	seq_printf(file, "Target power: %d\n", dev->target_power);
@@ -68,9 +68,9 @@ static const struct file_operations fops_ampdu_stat = { 
static int

mt76x2_dfs_stat_read(struct seq_file *file, void *data)

{

	struct mt76x02_dev *dev = file->private;

	struct mt76x02_dfs_pattern_detector *dfs_pd = &dev->dfs_pd;

	int i;

	struct mt76x2_dev *dev = file->private;

	struct mt76x2_dfs_pattern_detector *dfs_pd = &dev->dfs_pd;



	seq_printf(file, "allocated sequences:\t%d\n",

		   dfs_pd->seq_stats.seq_pool_len);
@@ -106,7 +106,7 @@ static const struct file_operations fops_dfs_stat = { 


static int read_agc(struct seq_file *file, void *data)

{

	struct mt76x2_dev *dev = dev_get_drvdata(file->private);

	struct mt76x02_dev *dev = dev_get_drvdata(file->private);



	seq_printf(file, "avg_rssi: %d\n", dev->cal.avg_rssi_all);

	seq_printf(file, "low_gain: %d\n", dev->cal.low_gain);
@@ -116,7 +116,7 @@ static int read_agc(struct seq_file *file, void *data) 
	return 0;

}



void mt76x2_init_debugfs(struct mt76x2_dev *dev)

void mt76x2_init_debugfs(struct mt76x02_dev *dev)

{

	struct dentry *dir;

drivers/net/wireless/mediatek/mt76/mt76x2/dfs.h

+7 −127
Original line number Diff line number Diff line
@@ -14,133 +14,13 @@ 
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

 */



#ifndef __MT76x2_DFS_H

#define __MT76x2_DFS_H

#ifndef __DFS_H

#define __DFS_H



#include <linux/types.h>

#include <linux/nl80211.h>



#define MT_DFS_GP_INTERVAL		(10 << 4) /* 64 us unit */

#define MT_DFS_NUM_ENGINES		4



/* bbp params */

#define MT_DFS_SYM_ROUND		0

#define MT_DFS_DELTA_DELAY		2

#define MT_DFS_VGA_MASK			0

#define MT_DFS_PWR_GAIN_OFFSET		3

#define MT_DFS_PWR_DOWN_TIME		0xf

#define MT_DFS_RX_PE_MASK		0xff

#define MT_DFS_PKT_END_MASK		0

#define MT_DFS_CH_EN			0xf



/* sw detector params */

#define MT_DFS_EVENT_LOOP		64

#define MT_DFS_SW_TIMEOUT		(HZ / 20)

#define MT_DFS_EVENT_WINDOW		(HZ / 5)

#define MT_DFS_SEQUENCE_WINDOW		(200 * (1 << 20))

#define MT_DFS_EVENT_TIME_MARGIN	2000

#define MT_DFS_PRI_MARGIN		4

#define MT_DFS_SEQUENCE_TH		6



#define MT_DFS_FCC_MAX_PRI		((28570 << 1) + 1000)

#define MT_DFS_FCC_MIN_PRI		(3000 - 2)

#define MT_DFS_JP_MAX_PRI		((80000 << 1) + 1000)

#define MT_DFS_JP_MIN_PRI		(28500 - 2)

#define MT_DFS_ETSI_MAX_PRI		(133333 + 125000 + 117647 + 1000)

#define MT_DFS_ETSI_MIN_PRI		(4500 - 20)



struct mt76x2_radar_specs {

	u8 mode;

	u16 avg_len;

	u16 e_low;

	u16 e_high;

	u16 w_low;

	u16 w_high;

	u16 w_margin;

	u32 t_low;

	u32 t_high;

	u16 t_margin;

	u32 b_low;

	u32 b_high;

	u32 event_expiration;

	u16 pwr_jmp;

};



#define MT_DFS_CHECK_EVENT(x)		((x) != GENMASK(31, 0))

#define MT_DFS_EVENT_ENGINE(x)		(((x) & BIT(31)) ? 2 : 0)

#define MT_DFS_EVENT_TIMESTAMP(x)	((x) & GENMASK(21, 0))

#define MT_DFS_EVENT_WIDTH(x)		((x) & GENMASK(11, 0))

struct mt76x2_dfs_event {

	unsigned long fetch_ts;

	u32 ts;

	u16 width;

	u8 engine;

};



#define MT_DFS_EVENT_BUFLEN		256

struct mt76x2_dfs_event_rb {

	struct mt76x2_dfs_event data[MT_DFS_EVENT_BUFLEN];

	int h_rb, t_rb;

};



struct mt76x2_dfs_sequence {

	struct list_head head;

	u32 first_ts;

	u32 last_ts;

	u32 pri;

	u16 count;

	u8 engine;

};



struct mt76x2_dfs_hw_pulse {

	u8 engine;

	u32 period;

	u32 w1;

	u32 w2;

	u32 burst;

};



struct mt76x2_dfs_sw_detector_params {

	u32 min_pri;

	u32 max_pri;

	u32 pri_margin;

};



struct mt76x2_dfs_engine_stats {

	u32 hw_pattern;

	u32 hw_pulse_discarded;

	u32 sw_pattern;

};



struct mt76x2_dfs_seq_stats {

	u32 seq_pool_len;

	u32 seq_len;

};



struct mt76x2_dfs_pattern_detector {

	enum nl80211_dfs_regions region;



	u8 chirp_pulse_cnt;

	u32 chirp_pulse_ts;



	struct mt76x2_dfs_sw_detector_params sw_dpd_params;

	struct mt76x2_dfs_event_rb event_rb[2];



	struct list_head sequences;

	struct list_head seq_pool;

	struct mt76x2_dfs_seq_stats seq_stats;



	unsigned long last_sw_check;

	u32 last_event_ts;



	struct mt76x2_dfs_engine_stats stats[MT_DFS_NUM_ENGINES];

	struct tasklet_struct dfs_tasklet;

};



void mt76x2_dfs_init_params(struct mt76x2_dev *dev);

void mt76x2_dfs_init_detector(struct mt76x2_dev *dev);

void mt76x2_dfs_adjust_agc(struct mt76x2_dev *dev);

void mt76x2_dfs_set_domain(struct mt76x2_dev *dev,

void mt76x2_dfs_init_params(struct mt76x02_dev *dev);

void mt76x2_dfs_init_detector(struct mt76x02_dev *dev);

void mt76x2_dfs_adjust_agc(struct mt76x02_dev *dev);

void mt76x2_dfs_set_domain(struct mt76x02_dev *dev,

			   enum nl80211_dfs_regions region);



#endif /* __MT76x2_DFS_H */
 
#endif /* __DFS_H */

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