Commit e3ff9114 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm 

Pull ARM fixes from Russell King:
 "Another round of ARM fixes.  Largest one is the second half of the
  PJ4B fix which was pushed in the previous -rc - this one was delayed
  because its original caused a build regression while trying to fix a
  regression!

  As ever, noMMU gets forgotten when fixing problems on MMU, so we have
  a noMMU fix for a previous fix included in this set.

  A couple of fixes from Lorenzo for problems with the ARM DT CPU code,
  and a one liner to remove the buggy 'wait for interrupt' with FA526
  cores"

* 'fixes' of git://git.linaro.org/people/rmk/linux-arm:
  ARM: 7773/1: PJ4B: Add support for errata 4742
  ARM: 7772/1: Fix missing flush_kernel_dcache_page() for noMMU
  ARM: 7763/1: kernel: fix __cpu_logical_map default initialization
  ARM: 7762/1: kernel: fix arm_dt_init_cpu_maps() to skip non-cpu nodes
  ARM: 7760/1: cpu_fa526_do_idle: remove WFI
parents de6e1317 3e0a07f8

arch/arm/Kconfig

+14 −0
Original line number Diff line number Diff line
@@ -1087,6 +1087,20 @@ if !MMU 
source "arch/arm/Kconfig-nommu"

endif



config PJ4B_ERRATA_4742

	bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"

	depends on CPU_PJ4B && MACH_ARMADA_370

	default y

	help

	  When coming out of either a Wait for Interrupt (WFI) or a Wait for

	  Event (WFE) IDLE states, a specific timing sensitivity exists between

	  the retiring WFI/WFE instructions and the newly issued subsequent

	  instructions.  This sensitivity can result in a CPU hang scenario.

	  Workaround:

	  The software must insert either a Data Synchronization Barrier (DSB)

	  or Data Memory Barrier (DMB) command immediately after the WFI/WFE

	  instruction



config ARM_ERRATA_326103

	bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"

	depends on CPU_V6

arch/arm/include/asm/cputype.h

+2 −0
Original line number Diff line number Diff line
@@ -32,6 +32,8 @@ 


#define MPIDR_HWID_BITMASK 0xFFFFFF



#define MPIDR_INVALID (~MPIDR_HWID_BITMASK)



#define MPIDR_LEVEL_BITS 8

#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)

arch/arm/include/asm/glue-proc.h

+9 −0
Original line number Diff line number Diff line
@@ -230,6 +230,15 @@ 
# endif

#endif



#ifdef CONFIG_CPU_PJ4B

# ifdef CPU_NAME

#  undef  MULTI_CPU

#  define MULTI_CPU

# else

#  define CPU_NAME cpu_pj4b

# endif

#endif



#ifndef MULTI_CPU

#define cpu_proc_init			__glue(CPU_NAME,_proc_init)

#define cpu_proc_fin			__glue(CPU_NAME,_proc_fin)

arch/arm/include/asm/smp_plat.h

+1 −1
Original line number Diff line number Diff line
@@ -49,7 +49,7 @@ static inline int cache_ops_need_broadcast(void) 
/*

 * Logical CPU mapping.

 */

extern int __cpu_logical_map[];

extern u32 __cpu_logical_map[];

#define cpu_logical_map(cpu)	__cpu_logical_map[cpu]

/*

 * Retrieve logical cpu index corresponding to a given MPIDR[23:0]

arch/arm/kernel/devtree.c

+4 −1
Original line number Diff line number Diff line
@@ -82,7 +82,7 @@ void __init arm_dt_init_cpu_maps(void) 
	u32 i, j, cpuidx = 1;

	u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;



	u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = UINT_MAX };

	u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };

	bool bootcpu_valid = false;

	cpus = of_find_node_by_path("/cpus");
@@ -92,6 +92,9 @@ void __init arm_dt_init_cpu_maps(void) 
	for_each_child_of_node(cpus, cpu) {

		u32 hwid;



		if (of_node_cmp(cpu->type, "cpu"))

			continue;



		pr_debug(" * %s...\n", cpu->full_name);

		/*

		 * A device tree containing CPU nodes with missing "reg"

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