Commit e3edd671 authored Apr 20, 2015 by Nishanth Menon Committed by Alexandre Belloni Jun 25, 2015

rtc: ds1307: Enable the mcp794xx alarm after programming time



Alarm interrupt enable register is at offset 0x7, while the time
registers for the alarm follow that. When we program Alarm interrupt
enable prior to programming the time, it is possible that previous
time value could be close or match at the time of alarm enable
resulting in interrupt trigger which is unexpected (and does not match
the time we expect it to trigger).

To prevent this scenario from occuring, program the ALM0_EN bit only
after the alarm time is appropriately programmed.

Ofcourse, I2C programming is non-atomic, so there are loopholes where
the interrupt wont trigger if the time requested is in the past at
the time of programming the ALM0_EN bit. However, we will not have
unexpected interrupts while the time is programmed after the interrupt
are enabled.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@linaro.org>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>

parent 4be1f6bb

drivers/rtc/rtc-ds1307.c

+6 −6

Original line number	Diff line number	Diff line
		@@ -742,17 +742,17 @@ static int mcp794xx_set_alarm(struct device dev, struct rtc_wkalrm t)
		regs[6] &= ~MCP794XX_BIT_ALMX_IF;
		/* Set alarm match: second, minute, hour, day, date, month. */
		regs[6] \|= MCP794XX_MSK_ALMX_MATCH;

		if (t->enabled)
		regs[0] \|= MCP794XX_BIT_ALM0_EN;
		else
		/* Disable interrupt. We will not enable until completely programmed */
		regs[0] &= ~MCP794XX_BIT_ALM0_EN;

		ret = ds1307->write_block_data(client, MCP794XX_REG_CONTROL, 10, regs);
		if (ret < 0)
		return ret;

		if (!t->enabled)
		return 0;
		regs[0] \|= MCP794XX_BIT_ALM0_EN;
		return i2c_smbus_write_byte_data(client, MCP794XX_REG_CONTROL, regs[0]);
		}

		static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)

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