drm/msm: Set the global virtual address range from the IOMMU domain (e3c64c72) · Commits · 戴 / test

drivers/gpu/drm/msm/adreno/adreno_gpu.c

+11 −2

Original line number	Diff line number	Diff line
		@@ -192,6 +192,7 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu,
		struct iommu_domain *iommu;
		struct msm_mmu *mmu;
		struct msm_gem_address_space *aspace;
		u64 start, size;

		iommu = iommu_domain_alloc(&platform_bus_type);
		if (!iommu)
		@@ -199,8 +200,16 @@ adreno_iommu_create_address_space(struct msm_gpu *gpu,

		mmu = msm_iommu_new(&pdev->dev, iommu);

		aspace = msm_gem_address_space_create(mmu, "gpu", SZ_16M,
		0xffffffff - SZ_16M);
		/*
		* Use the aperture start or SZ_16M, whichever is greater. This will
		* ensure that we align with the allocated pagetable range while still
		* allowing room in the lower 32 bits for GMEM and whatnot
		*/
		start = max_t(u64, SZ_16M, iommu->geometry.aperture_start);
		size = iommu->geometry.aperture_end - start + 1;

		aspace = msm_gem_address_space_create(mmu, "gpu",
		start & GENMASK(48, 0), size);

		if (IS_ERR(aspace) && !IS_ERR(mmu))
		mmu->funcs->destroy(mmu);

+7 −0

Original line number	Diff line number	Diff line
		@@ -36,6 +36,10 @@ static int msm_iommu_map(struct msm_mmu *mmu, uint64_t iova,
		struct msm_iommu *iommu = to_msm_iommu(mmu);
		size_t ret;

		/* The arm-smmu driver expects the addresses to be sign extended */
		if (iova & BIT_ULL(48))
		iova \|= GENMASK_ULL(63, 49);

		ret = iommu_map_sg(iommu->domain, iova, sgt->sgl, sgt->nents, prot);
		WARN_ON(!ret);

		@@ -46,6 +50,9 @@ static int msm_iommu_unmap(struct msm_mmu *mmu, uint64_t iova, size_t len)
		{
		struct msm_iommu *iommu = to_msm_iommu(mmu);

		if (iova & BIT_ULL(48))
		iova \|= GENMASK_ULL(63, 49);

		iommu_unmap(iommu->domain, iova, len);

		return 0;