Commit e3608799 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'zynq-cleanup-for-3.18' of git://git.xilinx.com/linux-xlnx into next/soc 



Pull "arm: Xilinx Zynq cleanup patches for v3.18" from Michal Simek:

- PM support
- Fix L2 useless setting

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>

* tag 'zynq-cleanup-for-3.18' of git://git.xilinx.com/linux-xlnx:
  ARM: zynq: Remove useless L2C AUX setting
  ARM: zynq: Rename 'zynq_platform_cpu_die'
  ARM: zynq: Remove hotplug.c
  ARM: zynq: Synchronise zynq_cpu_die/kill
  ARM: zynq: cpuidle: Remove pointless code
  ARM: zynq: Remove invalidate cache for cpu die
  ARM: zynq: PM: Enable DDR clock stop
  ARM: zynq: DT: Add DDRC node
  Documentation: devicetree: Add binding for Synopsys DDR controller
  ARM: zynq: PM: Enable A9 internal clock gating feature
parents 3b8f5030 8097171e

Documentation/devicetree/bindings/memory-controllers/synopsys.txt

0 → 100644
+11 −0
Original line number Diff line number Diff line 
Binding for Synopsys IntelliDDR Multi Protocol Memory Controller



Required properties:

 - compatible: Should be 'xlnx,zynq-ddrc-a05'

 - reg: Base address and size of the controllers memory area



Example:

	memory-controller@f8006000 {

		compatible = "xlnx,zynq-ddrc-a05";

		reg = <0xf8006000 0x1000>;

	};

arch/arm/boot/dts/zynq-7000.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -146,6 +146,11 @@ 
			cache-level = <2>;

		};



		memory-controller@f8006000 {

			compatible = "xlnx,zynq-ddrc-a05";

			reg = <0xf8006000 0x1000>;

		} ;



		uart0: serial@e0000000 {

			compatible = "xlnx,xuartps", "cdns,uart-r1p8";

			status = "disabled";

arch/arm/mach-zynq/Makefile

+1 −2
Original line number Diff line number Diff line
@@ -3,8 +3,7 @@ 
#



# Common support

obj-y				:= common.o slcr.o

obj-y				:= common.o slcr.o pm.o

CFLAGS_REMOVE_hotplug.o		=-march=armv6k

CFLAGS_hotplug.o 		=-Wa,-march=armv7-a -mcpu=cortex-a9

obj-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o

obj-$(CONFIG_SMP)		+= headsmp.o platsmp.o

arch/arm/mach-zynq/common.c

+9 −2
Original line number Diff line number Diff line
@@ -98,6 +98,12 @@ static int __init zynq_get_revision(void) 
	return revision;

}



static void __init zynq_init_late(void)

{

	zynq_core_pm_init();

	zynq_pm_late_init();

}



/**

 * zynq_init_machine - System specific initialization, intended to be

 *		       called from board specific initialization.
@@ -198,12 +204,13 @@ static const char * const zynq_dt_match[] = { 


DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")

	/* 64KB way size, 8-way associativity, parity disabled */

	.l2c_aux_val	= 0x02000000,

	.l2c_aux_mask	= 0xf0ffffff,

	.l2c_aux_val	= 0x00000000,

	.l2c_aux_mask	= 0xffffffff,

	.smp		= smp_ops(zynq_smp_ops),

	.map_io		= zynq_map_io,

	.init_irq	= zynq_irq_init,

	.init_machine	= zynq_init_machine,

	.init_late	= zynq_init_late,

	.init_time	= zynq_timer_init,

	.dt_compat	= zynq_dt_match,

	.reserve	= zynq_memory_init,

arch/arm/mach-zynq/common.h

+14 −2
Original line number Diff line number Diff line
@@ -24,6 +24,8 @@ extern int zynq_early_slcr_init(void); 
extern void zynq_slcr_system_reset(void);

extern void zynq_slcr_cpu_stop(int cpu);

extern void zynq_slcr_cpu_start(int cpu);

extern bool zynq_slcr_cpu_state_read(int cpu);

extern void zynq_slcr_cpu_state_write(int cpu, bool die);

extern u32 zynq_slcr_get_device_id(void);



#ifdef CONFIG_SMP
@@ -37,7 +39,17 @@ extern struct smp_operations zynq_smp_ops __initdata; 


extern void __iomem *zynq_scu_base;



/* Hotplug */

extern void zynq_platform_cpu_die(unsigned int cpu);

void zynq_pm_late_init(void);



static inline void zynq_core_pm_init(void)

{

	/* A9 clock gating */

	asm volatile ("mrc  p15, 0, r12, c15, c0, 0\n"

		      "orr  r12, r12, #1\n"

		      "mcr  p15, 0, r12, c15, c0, 0\n"

		      : /* no outputs */

		      : /* no inputs */

		      : "r12");

}



#endif

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