Commit e34eb39c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

* 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86, amd: Include linux/elf.h since we use stuff from asm/elf.h
  x86: cache_info: Update calculation of AMD L3 cache indices
  x86: cache_info: Kill the atomic allocation in amd_init_l3_cache()
  x86: cache_info: Kill the moronic shadow struct
  x86: cache_info: Remove bogus free of amd_l3_cache data
  x86, amd: Include elf.h explicitly, prepare the code for the module.h split
  x86-32, amd: Move va_align definition to unbreak 32-bit build
  x86, amd: Move BSP code to cpu_dev helper
  x86: Add a BSP cpu_dev helper
  x86, amd: Avoid cache aliasing penalties on AMD family 15h
parents 396e6e49 910b2c51

Documentation/kernel-parameters.txt

+13 −0
Original line number Diff line number Diff line
@@ -307,6 +307,19 @@ bytes respectively. Such letter suffixes can also be entirely omitted. 
			behaviour to be specified.  Bit 0 enables warnings,

			bit 1 enables fixups, and bit 2 sends a segfault.



	align_va_addr=	[X86-64]

			Align virtual addresses by clearing slice [14:12] when

			allocating a VMA at process creation time. This option

			gives you up to 3% performance improvement on AMD F15h

			machines (where it is enabled by default) for a

			CPU-intensive style benchmark, and it can vary highly in

			a microbenchmark depending on workload and compiler.



			1: only for 32-bit processes

			2: only for 64-bit processes

			on: enable for both 32- and 64-bit processes

			off: disable for both 32- and 64-bit processes



	amd_iommu=	[HW,X86-84]

			Pass parameters to the AMD IOMMU driver in the system.

			Possible values are:

arch/x86/include/asm/amd_nb.h

+6 −0
Original line number Diff line number Diff line
@@ -19,9 +19,15 @@ extern int amd_numa_init(void); 
extern int amd_get_subcaches(int);

extern int amd_set_subcaches(int, int);



struct amd_l3_cache {

	unsigned indices;

	u8	 subcaches[4];

};



struct amd_northbridge {

	struct pci_dev *misc;

	struct pci_dev *link;

	struct amd_l3_cache l3_cache;

};



struct amd_northbridge_info {

arch/x86/include/asm/elf.h

+31 −0
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
/*

 * ELF register definitions..

 */

#include <linux/thread_info.h>



#include <asm/ptrace.h>

#include <asm/user.h>
@@ -320,4 +321,34 @@ extern int syscall32_setup_pages(struct linux_binprm *, int exstack); 
extern unsigned long arch_randomize_brk(struct mm_struct *mm);

#define arch_randomize_brk arch_randomize_brk



/*

 * True on X86_32 or when emulating IA32 on X86_64

 */

static inline int mmap_is_ia32(void)

{

#ifdef CONFIG_X86_32

	return 1;

#endif

#ifdef CONFIG_IA32_EMULATION

	if (test_thread_flag(TIF_IA32))

		return 1;

#endif

	return 0;

}



/* The first two values are special, do not change. See align_addr() */

enum align_flags {

	ALIGN_VA_32	= BIT(0),

	ALIGN_VA_64	= BIT(1),

	ALIGN_VDSO	= BIT(2),

	ALIGN_TOPDOWN	= BIT(3),

};



struct va_alignment {

	int flags;

	unsigned long mask;

} ____cacheline_aligned;



extern struct va_alignment va_align;

extern unsigned long align_addr(unsigned long, struct file *, enum align_flags);

#endif /* _ASM_X86_ELF_H */

arch/x86/kernel/cpu/amd.c

+30 −17
Original line number Diff line number Diff line 
#include <linux/init.h>

#include <linux/bitops.h>

#include <linux/elf.h>

#include <linux/mm.h>



#include <linux/io.h>
@@ -410,6 +411,34 @@ static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c) 
#endif

}



static void __cpuinit bsp_init_amd(struct cpuinfo_x86 *c)

{

	if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {



		if (c->x86 > 0x10 ||

		    (c->x86 == 0x10 && c->x86_model >= 0x2)) {

			u64 val;



			rdmsrl(MSR_K7_HWCR, val);

			if (!(val & BIT(24)))

				printk(KERN_WARNING FW_BUG "TSC doesn't count "

					"with P0 frequency!\n");

		}

	}



	if (c->x86 == 0x15) {

		unsigned long upperbit;

		u32 cpuid, assoc;



		cpuid	 = cpuid_edx(0x80000005);

		assoc	 = cpuid >> 16 & 0xff;

		upperbit = ((cpuid >> 24) << 10) / assoc;



		va_align.mask	  = (upperbit - 1) & PAGE_MASK;

		va_align.flags    = ALIGN_VA_32 | ALIGN_VA_64;

	}

}



static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)

{

	early_init_amd_mc(c);
@@ -441,23 +470,6 @@ static void __cpuinit early_init_amd(struct cpuinfo_x86 *c) 
			set_cpu_cap(c, X86_FEATURE_EXTD_APICID);

	}

#endif



	/* We need to do the following only once */

	if (c != &boot_cpu_data)

		return;



	if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {



		if (c->x86 > 0x10 ||

		    (c->x86 == 0x10 && c->x86_model >= 0x2)) {

			u64 val;



			rdmsrl(MSR_K7_HWCR, val);

			if (!(val & BIT(24)))

				printk(KERN_WARNING FW_BUG "TSC doesn't count "

					"with P0 frequency!\n");

		}

	}

}



static void __cpuinit init_amd(struct cpuinfo_x86 *c)
@@ -679,6 +691,7 @@ static const struct cpu_dev __cpuinitconst amd_cpu_dev = { 
	.c_size_cache	= amd_size_cache,

#endif

	.c_early_init   = early_init_amd,

	.c_bsp_init	= bsp_init_amd,

	.c_init		= init_amd,

	.c_x86_vendor	= X86_VENDOR_AMD,

};

arch/x86/kernel/cpu/common.c

+3 −0
Original line number Diff line number Diff line
@@ -681,6 +681,9 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c) 
	filter_cpuid_features(c, false);



	setup_smep(c);



	if (this_cpu->c_bsp_init)

		this_cpu->c_bsp_init(c);

}



void __init early_cpu_init(void)

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