Commit e347afa5 authored by Ji-Ze Hong (Peter Hong)'s avatar Ji-Ze Hong (Peter Hong) Committed by Wim Van Sebroeck
Browse files

watchdog: f71808e_wdt: fix F81866 bit operation 



Fix error bit operation in watchdog_start()

Fixes: 14b24a88 ("watchdog: f71808e_wdt: Add F81866 support")
Signed-off-by: default avatarJi-Ze Hong (Peter Hong) <hpeter+linux_kernel@gmail.com>
Reviewed-by: default avatarGuenter Roeck <linux@roeck-us.net>
Signed-off-by: default avatarGuenter Roeck <linux@roeck-us.net>
Signed-off-by: default avatarWim Van Sebroeck <wim@linux-watchdog.org>
parent a3f764d2

drivers/watchdog/f71808e_wdt.c

+7 −7
Original line number Diff line number Diff line
@@ -339,6 +339,7 @@ static int f71862fg_pin_configure(unsigned short ioaddr) 
static int watchdog_start(void)

{

	int err;

	u8 tmp;



	/* Make sure we don't die as soon as the watchdog is enabled below */

	err = watchdog_keepalive();
@@ -388,19 +389,18 @@ static int watchdog_start(void) 
		break;



	case f81866:

		/* Set pin 70 to WDTRST# */

		superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL,

				  BIT(3) | BIT(0));

		superio_set_bit(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL,

				BIT(2));

		/*

		 * GPIO1 Control Register when 27h BIT3:2 = 01 & BIT0 = 0.

		 * The PIN 70(GPIO15/WDTRST) is controlled by 2Ch:

		 *     BIT5: 0 -> WDTRST#

		 *           1 -> GPIO15

		 */

		superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_GPIO1,

				  BIT(5));

		tmp = superio_inb(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL);

		tmp &= ~(BIT(3) | BIT(0));

		tmp |= BIT(2);

		superio_outb(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL, tmp);



		superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_GPIO1, 5);

		break;



	default:

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