Commit e3455133 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu 

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (41 commits)
  m68knommu: external interrupt support to ColdFire intc-simr controller
  m68knommu: external interrupt support to ColdFire intc-2 controller
  m68knommu: remove ColdFire CLOCK_DIV config option
  m68knommu: fix gpio warnings for ColdFire 5407 targets
  m68knommu: fix gpio warnings for ColdFire 532x targets
  m68knommu: fix gpio warnings for ColdFire 5307 targets
  m68knommu: fix gpio warnings for ColdFire 527x targets
  m68knommu: fix gpio warnings for ColdFire 5272 targets
  m68knommu: fix gpio warnings for ColdFire 5249 targets
  m68knommu: fix gpio warnings for ColdFire 523x targets
  m68knommu: fix gpio warnings for ColdFire 520x targets
  m68knommu: fix gpio warnings for ColdFire 5206e targets
  m68knommu: fix gpio warnings for ColdFire 5206 targets
  m68knommu: fixing compiler warnings
  m68knommu: limit interrupts supported by ColdFire intc-simr driver
  m68knommu: move some init code out of unmask routine for ColdFire intc-2
  m68knommu: limit interrupts supported by ColdFire intc-2 driver
  m68knommu: add basic support for the ColdFire based FireBee board
  m68knommu: make ColdFire internal peripheral region configurable
  m68knommu: clean up definitions of ColdFire peripheral base registers
  ...
parents 242e5d06 47e0c7e1

arch/m68k/include/asm/coldfire.h

+19 −23
Original line number Diff line number Diff line
@@ -14,39 +14,35 @@ 




/*

 *	Define master clock frequency. This is essentially done at config

 *	time now. No point enumerating dozens of possible clock options

 *	here. Also the peripheral clock (bus clock) divide ratio is set

 *	at config time too.

 *	Define master clock frequency. This is done at config time now.

 *	No point enumerating dozens of possible clock options here. And

 *	in any case new boards come along from time to time that have yet

 *	another different clocking frequency.

 */

#ifdef CONFIG_CLOCK_SET

#define	MCF_CLK		CONFIG_CLOCK_FREQ

#define	MCF_BUSCLK	(CONFIG_CLOCK_FREQ / CONFIG_CLOCK_DIV)

#else

#error "Don't know what your ColdFire CPU clock frequency is??"

#endif



/*

 *	Define the processor support peripherals base address.

 *	This is generally setup by the boards start up code.

 *	Define the processor internal peripherals base address.

 *

 *	The majority of ColdFire parts use an MBAR register to set

 *	the base address. Some have an IPSBAR register instead, and it

 *	has slightly different rules on its size and alignment. Some

 *	parts have fixed addresses and the internal peripherals cannot

 *	be relocated in the CPU address space.

 *

 *	The value of MBAR or IPSBAR is config time selectable, we no

 *	longer hard define it here. No MBAR or IPSBAR will be defined if

 *	this part has a fixed peripheral address map.

 */

#define	MCF_MBAR	0x10000000

#define	MCF_MBAR2	0x80000000

#if defined(CONFIG_M54xx)

#define	MCF_IPSBAR	MCF_MBAR

#elif defined(CONFIG_M520x)

#define	MCF_IPSBAR	0xFC000000

#else

#define	MCF_IPSBAR	0x40000000

#ifdef CONFIG_MBAR

#define	MCF_MBAR	CONFIG_MBAR

#endif



#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \

    defined(CONFIG_M520x)

#undef MCF_MBAR

#define	MCF_MBAR	MCF_IPSBAR

#elif defined(CONFIG_M532x)

#undef MCF_MBAR

#define MCF_MBAR	0x00000000

#ifdef CONFIG_IPSBAR

#define	MCF_IPSBAR	CONFIG_IPSBAR

#endif



/****************************************************************************/

arch/m68k/include/asm/m5206sim.h

+15 −8
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 


#define	CPU_NAME		"COLDFIRE(m5206)"

#define	CPU_INSTR_PER_JIFFY	3

#define	MCF_BUSCLK		MCF_CLK



#include <asm/m52xxacr.h>
@@ -48,14 +49,14 @@ 
#define	MCFSIM_SWIVR		0x42		/* SW Watchdog intr reg (r/w) */

#define	MCFSIM_SWSR		0x43		/* SW Watchdog service (r/w) */



#define	MCFSIM_DCRR		0x46		/* DRAM Refresh reg (r/w) */

#define	MCFSIM_DCTR		0x4a		/* DRAM Timing reg (r/w) */

#define	MCFSIM_DAR0		0x4c		/* DRAM 0 Address reg(r/w) */

#define	MCFSIM_DMR0		0x50		/* DRAM 0 Mask reg (r/w) */

#define	MCFSIM_DCR0		0x57		/* DRAM 0 Control reg (r/w) */

#define	MCFSIM_DAR1		0x58		/* DRAM 1 Address reg (r/w) */

#define	MCFSIM_DMR1		0x5c		/* DRAM 1 Mask reg (r/w) */

#define	MCFSIM_DCR1		0x63		/* DRAM 1 Control reg (r/w) */

#define	MCFSIM_DCRR		(MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */

#define	MCFSIM_DCTR		(MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */

#define	MCFSIM_DAR0		(MCF_MBAR + 0x4c) /* DRAM 0 Address reg(r/w) */

#define	MCFSIM_DMR0		(MCF_MBAR + 0x50) /* DRAM 0 Mask reg (r/w) */

#define	MCFSIM_DCR0		(MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */

#define	MCFSIM_DAR1		(MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */

#define	MCFSIM_DMR1		(MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */

#define	MCFSIM_DCR1		(MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */



#define	MCFSIM_CSAR0		0x64		/* CS 0 Address 0 reg (r/w) */

#define	MCFSIM_CSMR0		0x68		/* CS 0 Mask 0 reg (r/w) */
@@ -89,9 +90,15 @@ 
#define	MCFSIM_PAR		0xcb		/* Pin Assignment reg (r/w) */

#endif



#define	MCFTIMER_BASE1		(MCF_MBAR + 0x100)	/* Base of TIMER1 */

#define	MCFTIMER_BASE2		(MCF_MBAR + 0x120)	/* Base of TIMER2 */



#define	MCFSIM_PADDR		(MCF_MBAR + 0x1c5)	/* Parallel Direction (r/w) */

#define	MCFSIM_PADAT		(MCF_MBAR + 0x1c9)	/* Parallel Port Value (r/w) */



#define	MCFDMA_BASE0		(MCF_MBAR + 0x200)	/* Base address DMA 0 */

#define	MCFDMA_BASE1		(MCF_MBAR + 0x240)	/* Base address DMA 1 */



#if defined(CONFIG_NETtel)

#define	MCFUART_BASE1		0x180		/* Base address of UART1 */

#define	MCFUART_BASE2		0x140		/* Base address of UART2 */

arch/m68k/include/asm/m520xsim.h

+33 −17
Original line number Diff line number Diff line
@@ -13,13 +13,14 @@ 


#define	CPU_NAME		"COLDFIRE(m520x)"

#define	CPU_INSTR_PER_JIFFY	3

#define	MCF_BUSCLK		(MCF_CLK / 2)



#include <asm/m52xxacr.h>



/*

 *  Define the 520x SIM register set addresses.

 */

#define MCFICM_INTC0        0x48000     /* Base for Interrupt Ctrl 0 */

#define MCFICM_INTC0        0xFC048000  /* Base for Interrupt Ctrl 0 */

#define MCFINTC_IPRH        0x00        /* Interrupt pending 32-63 */

#define MCFINTC_IPRL        0x04        /* Interrupt pending 1-31 */

#define MCFINTC_IMRH        0x08        /* Interrupt mask 32-63 */
@@ -35,9 +36,9 @@ 
 *  address to the SIMR and CIMR registers (not offsets into IPSBAR).

 *  The 520x family only has a single INTC unit.

 */

#define MCFINTC0_SIMR       (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_SIMR)

#define MCFINTC0_CIMR       (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_CIMR)

#define	MCFINTC0_ICR0       (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0)

#define MCFINTC0_SIMR       (MCFICM_INTC0 + MCFINTC_SIMR)

#define MCFINTC0_CIMR       (MCFICM_INTC0 + MCFINTC_CIMR)

#define	MCFINTC0_ICR0       (MCFICM_INTC0 + MCFINTC_ICR0)

#define MCFINTC1_SIMR       (0)

#define MCFINTC1_CIMR       (0)

#define	MCFINTC1_ICR0       (0)
@@ -52,19 +53,22 @@ 
/*

 *  SDRAM configuration registers.

 */

#define MCFSIM_SDMR         0x000a8000	/* SDRAM Mode/Extended Mode Register */

#define MCFSIM_SDCR         0x000a8004	/* SDRAM Control Register */

#define MCFSIM_SDCFG1       0x000a8008	/* SDRAM Configuration Register 1 */

#define MCFSIM_SDCFG2       0x000a800c	/* SDRAM Configuration Register 2 */

#define MCFSIM_SDCS0        0x000a8110	/* SDRAM Chip Select 0 Configuration */

#define MCFSIM_SDCS1        0x000a8114	/* SDRAM Chip Select 1 Configuration */

#define MCFSIM_SDMR         0xFC0a8000	/* SDRAM Mode/Extended Mode Register */

#define MCFSIM_SDCR         0xFC0a8004	/* SDRAM Control Register */

#define MCFSIM_SDCFG1       0xFC0a8008	/* SDRAM Configuration Register 1 */

#define MCFSIM_SDCFG2       0xFC0a800c	/* SDRAM Configuration Register 2 */

#define MCFSIM_SDCS0        0xFC0a8110	/* SDRAM Chip Select 0 Configuration */

#define MCFSIM_SDCS1        0xFC0a8114	/* SDRAM Chip Select 1 Configuration */



/*

 * EPORT and GPIO registers.

 */

#define MCFEPORT_EPPAR			0xFC088000

#define MCFEPORT_EPDDR			0xFC088002

#define MCFEPORT_EPIER			0xFC088003

#define MCFEPORT_EPDR			0xFC088004

#define MCFEPORT_EPPDR			0xFC088005

#define MCFEPORT_EPFR			0xFC088006



#define MCFGPIO_PODR_BUSCTL		0xFC0A4000

#define MCFGPIO_PODR_BE			0xFC0A4001
@@ -119,10 +123,10 @@ 
#define MCFGPIO_IRQ_MAX			8

#define MCFGPIO_IRQ_VECBASE		MCFINT_VECBASE



#define MCF_GPIO_PAR_UART                   (0xA4036)

#define MCF_GPIO_PAR_FECI2C                 (0xA4033)

#define MCF_GPIO_PAR_QSPI                   (0xA4034)

#define MCF_GPIO_PAR_FEC                    (0xA4038)

#define MCF_GPIO_PAR_UART		0xFC0A4036

#define MCF_GPIO_PAR_FECI2C		0xFC0A4033

#define MCF_GPIO_PAR_QSPI		0xFC0A4034

#define MCF_GPIO_PAR_FEC		0xFC0A4038



#define MCF_GPIO_PAR_UART_PAR_URXD0         (0x0001)

#define MCF_GPIO_PAR_UART_PAR_UTXD0         (0x0002)
@@ -133,12 +137,24 @@ 
#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2   (0x02)

#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2   (0x04)



/*

 *  PIT timer module.

 */

#define	MCFPIT_BASE1		0xFC080000	/* Base address of TIMER1 */

#define	MCFPIT_BASE2		0xFC084000	/* Base address of TIMER2 */



/*

 *  UART module.

 */

#define MCFUART_BASE1		0x60000		/* Base address of UART1 */

#define MCFUART_BASE2		0x64000		/* Base address of UART2 */

#define MCFUART_BASE3		0x68000		/* Base address of UART2 */

#define MCFUART_BASE1		0xFC060000	/* Base address of UART1 */

#define MCFUART_BASE2		0xFC064000	/* Base address of UART2 */

#define MCFUART_BASE3		0xFC068000	/* Base address of UART2 */



/*

 *  FEC module.

 */

#define	MCFFEC_BASE		0xFC030000	/* Base of FEC ethernet */

#define	MCFFEC_SIZE		0x800		/* Register set size */



/*

 *  Reset Controll Unit.

arch/m68k/include/asm/m523xsim.h

+41 −11
Original line number Diff line number Diff line
@@ -13,14 +13,16 @@ 


#define	CPU_NAME		"COLDFIRE(m523x)"

#define	CPU_INSTR_PER_JIFFY	3

#define	MCF_BUSCLK		(MCF_CLK / 2)



#include <asm/m52xxacr.h>



/*

 *	Define the 523x SIM register set addresses.

 */

#define	MCFICM_INTC0		0x0c00		/* Base for Interrupt Ctrl 0 */

#define	MCFICM_INTC1		0x0d00		/* Base for Interrupt Ctrl 0 */

#define	MCFICM_INTC0		(MCF_IPSBAR + 0x0c00)	/* Base for Interrupt Ctrl 0 */

#define	MCFICM_INTC1		(MCF_IPSBAR + 0x0d00)	/* Base for Interrupt Ctrl 0 */



#define	MCFINTC_IPRH		0x00		/* Interrupt pending 32-63 */

#define	MCFINTC_IPRL		0x04		/* Interrupt pending 1-31 */

#define	MCFINTC_IMRH		0x08		/* Interrupt mask 32-63 */
@@ -39,11 +41,11 @@ 
/*

 *	SDRAM configuration registers.

 */

#define	MCFSIM_DCR		0x44		/* SDRAM control */

#define	MCFSIM_DACR0		0x48		/* SDRAM base address 0 */

#define	MCFSIM_DMR0		0x4c		/* SDRAM address mask 0 */

#define	MCFSIM_DACR1		0x50		/* SDRAM base address 1 */

#define	MCFSIM_DMR1		0x54		/* SDRAM address mask 1 */

#define	MCFSIM_DCR		(MCF_IPSBAR + 0x44)	/* Control */

#define	MCFSIM_DACR0		(MCF_IPSBAR + 0x48)	/* Base address 0 */

#define	MCFSIM_DMR0		(MCF_IPSBAR + 0x4c)	/* Address mask 0 */

#define	MCFSIM_DACR1		(MCF_IPSBAR + 0x50)	/* Base address 1 */

#define	MCFSIM_DMR1		(MCF_IPSBAR + 0x54)	/* Address mask 1 */



/*

 *  Reset Controll Unit (relative to IPSBAR).
@@ -57,10 +59,19 @@ 
/*

 *  UART module.

 */

#define MCFUART_BASE1		0x200           /* Base address of UART1 */

#define MCFUART_BASE2		0x240           /* Base address of UART2 */

#define MCFUART_BASE3		0x280           /* Base address of UART3 */

#define MCFUART_BASE1		(MCF_IPSBAR + 0x200)

#define MCFUART_BASE2		(MCF_IPSBAR + 0x240)

#define MCFUART_BASE3		(MCF_IPSBAR + 0x280)



/*

 *  FEC ethernet module.

 */

#define	MCFFEC_BASE		(MCF_IPSBAR + 0x1000)

#define	MCFFEC_SIZE		0x800



/*

 *  GPIO module.

 */

#define MCFGPIO_PODR_ADDR	(MCF_IPSBAR + 0x100000)

#define MCFGPIO_PODR_DATAH	(MCF_IPSBAR + 0x100001)

#define MCFGPIO_PODR_DATAL	(MCF_IPSBAR + 0x100002)
@@ -118,12 +129,22 @@ 
#define MCFGPIO_PCLRR_ETPU	(MCF_IPSBAR + 0x10003C)



/*

 * EPort

 * PIT timer base addresses.

 */

#define	MCFPIT_BASE1		(MCF_IPSBAR + 0x150000)

#define	MCFPIT_BASE2		(MCF_IPSBAR + 0x160000)

#define	MCFPIT_BASE3		(MCF_IPSBAR + 0x170000)

#define	MCFPIT_BASE4		(MCF_IPSBAR + 0x180000)



/*

 * EPort

 */

#define MCFEPORT_EPPAR		(MCF_IPSBAR + 0x130000)

#define MCFEPORT_EPDDR		(MCF_IPSBAR + 0x130002)

#define MCFEPORT_EPIER		(MCF_IPSBAR + 0x130003)

#define MCFEPORT_EPDR		(MCF_IPSBAR + 0x130004)

#define MCFEPORT_EPPDR		(MCF_IPSBAR + 0x130005)

#define MCFEPORT_EPFR		(MCF_IPSBAR + 0x130006)



/*

 * Generic GPIO support
@@ -143,5 +164,14 @@ 
*/

#define	MCFGPIO_PAR_QSPI	(MCF_IPSBAR + 0x10004A)

#define	MCFGPIO_PAR_TIMER	(MCF_IPSBAR + 0x10004C)



/*

 * DMA unit base addresses.

 */

#define	MCFDMA_BASE0		(MCF_IPSBAR + 0x100)

#define	MCFDMA_BASE1		(MCF_IPSBAR + 0x140)

#define	MCFDMA_BASE2		(MCF_IPSBAR + 0x180)

#define	MCFDMA_BASE3		(MCF_IPSBAR + 0x1C0)



/****************************************************************************/

#endif	/* m523xsim_h */

arch/m68k/include/asm/m5249sim.h

+25 −5
Original line number Diff line number Diff line
@@ -13,9 +13,15 @@ 


#define	CPU_NAME		"COLDFIRE(m5249)"

#define	CPU_INSTR_PER_JIFFY	3

#define	MCF_BUSCLK		(MCF_CLK / 2)



#include <asm/m52xxacr.h>



/*

 *	The 5249 has a second MBAR region, define its address.

 */

#define MCF_MBAR2		0x80000000



/*

 *	Define the 5249 SIM register set addresses.

 */
@@ -55,11 +61,17 @@ 
#define MCFSIM_CSMR3		0xa8		/* CS 3 Mask reg (r/w) */

#define MCFSIM_CSCR3		0xae		/* CS 3 Control reg (r/w) */



#define MCFSIM_DCR		0x100		/* DRAM Control reg (r/w) */

#define MCFSIM_DACR0		0x108		/* DRAM 0 Addr and Ctrl (r/w) */

#define MCFSIM_DMR0		0x10c		/* DRAM 0 Mask reg (r/w) */

#define MCFSIM_DACR1		0x110		/* DRAM 1 Addr and Ctrl (r/w) */

#define MCFSIM_DMR1		0x114		/* DRAM 1 Mask reg (r/w) */

#define MCFSIM_DCR		(MCF_MBAR + 0x100)	/* DRAM Control */

#define MCFSIM_DACR0		(MCF_MBAR + 0x108)	/* DRAM 0 Addr/Ctrl */

#define MCFSIM_DMR0		(MCF_MBAR + 0x10c)	/* DRAM 0 Mask */

#define MCFSIM_DACR1		(MCF_MBAR + 0x110)	/* DRAM 1 Addr/Ctrl */

#define MCFSIM_DMR1		(MCF_MBAR + 0x114)	/* DRAM 1 Mask */



/*

 *	Timer module.

 */

#define MCFTIMER_BASE1		(MCF_MBAR + 0x140)	/* Base of TIMER1 */

#define MCFTIMER_BASE2		(MCF_MBAR + 0x180)	/* Base of TIMER2 */



/*

 *	UART module.
@@ -67,6 +79,14 @@ 
#define MCFUART_BASE1		0x1c0           /* Base address of UART1 */

#define MCFUART_BASE2		0x200           /* Base address of UART2 */



/*

 *	DMA unit base addresses.

 */

#define MCFDMA_BASE0		(MCF_MBAR + 0x300)	/* Base address DMA 0 */

#define MCFDMA_BASE1		(MCF_MBAR + 0x340)	/* Base address DMA 1 */

#define MCFDMA_BASE2		(MCF_MBAR + 0x380)	/* Base address DMA 2 */

#define MCFDMA_BASE3		(MCF_MBAR + 0x3C0)	/* Base address DMA 3 */



/*

 *	Some symbol defines for the above...

 */

CRA Git | Maintained and supported by SUSTech CRA and CCSE