Commit e329ef67 authored by Rodrigo Vivi's avatar Rodrigo Vivi
Browse files

Merge tag 'gvt-next-2017-12-22' of https://github.com/intel/gvt-linux into drm-intel-next-queued 



gvt-next-2017-12-22:

- more mmio switch optimization (Weinan)
- cleanup i915_reg_t vs. offset usage (Zhenyu)
- move write protect handler out of mmio handler (Zhenyu)

Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171222085141.vgewlvvni37dljdt@zhen-hp.sh.intel.com
parents 757fffcf 4fafba2d

drivers/gpu/drm/i915/gvt/cmd_parser.c

+29 −10
Original line number Diff line number Diff line
@@ -825,6 +825,21 @@ static int force_nonpriv_reg_handler(struct parser_exec_state *s, 
	return 0;

}



static inline bool is_mocs_mmio(unsigned int offset)

{

	return ((offset >= 0xc800) && (offset <= 0xcff8)) ||

		((offset >= 0xb020) && (offset <= 0xb0a0));

}



static int mocs_cmd_reg_handler(struct parser_exec_state *s,

				unsigned int offset, unsigned int index)

{

	if (!is_mocs_mmio(offset))

		return -EINVAL;

	vgpu_vreg(s->vgpu, offset) = cmd_val(s, index + 1);

	return 0;

}



static int cmd_reg_handler(struct parser_exec_state *s,

	unsigned int offset, unsigned int index, char *cmd)

{
@@ -848,6 +863,10 @@ static int cmd_reg_handler(struct parser_exec_state *s, 
		return 0;

	}



	if (is_mocs_mmio(offset) &&

	    mocs_cmd_reg_handler(s, offset, index))

		return -EINVAL;



	if (is_force_nonpriv_mmio(offset) &&

		force_nonpriv_reg_handler(s, offset, index))

		return -EPERM;
@@ -1220,13 +1239,13 @@ static int gen8_check_mi_display_flip(struct parser_exec_state *s, 
		return 0;



	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {

		stride = vgpu_vreg(s->vgpu, info->stride_reg) & GENMASK(9, 0);

		tile = (vgpu_vreg(s->vgpu, info->ctrl_reg) &

		stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);

		tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &

				GENMASK(12, 10)) >> 10;

	} else {

		stride = (vgpu_vreg(s->vgpu, info->stride_reg) &

		stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &

				GENMASK(15, 6)) >> 6;

		tile = (vgpu_vreg(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;

		tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;

	}



	if (stride != info->stride_val)
@@ -1245,21 +1264,21 @@ static int gen8_update_plane_mmio_from_mi_display_flip( 
	struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;

	struct intel_vgpu *vgpu = s->vgpu;



	set_mask_bits(&vgpu_vreg(vgpu, info->surf_reg), GENMASK(31, 12),

	set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),

		      info->surf_val << 12);

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {

		set_mask_bits(&vgpu_vreg(vgpu, info->stride_reg), GENMASK(9, 0),

		set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),

			      info->stride_val);

		set_mask_bits(&vgpu_vreg(vgpu, info->ctrl_reg), GENMASK(12, 10),

		set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),

			      info->tile_val << 10);

	} else {

		set_mask_bits(&vgpu_vreg(vgpu, info->stride_reg), GENMASK(15, 6),

		set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),

			      info->stride_val << 6);

		set_mask_bits(&vgpu_vreg(vgpu, info->ctrl_reg), GENMASK(10, 10),

		set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),

			      info->tile_val << 10);

	}



	vgpu_vreg(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++;

	vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(info->pipe))++;

	intel_vgpu_trigger_virtual_event(vgpu, info->event);

	return 0;

}

drivers/gpu/drm/i915/gvt/display.c

+41 −40
Original line number Diff line number Diff line
@@ -59,7 +59,7 @@ static int edp_pipe_is_enabled(struct intel_vgpu *vgpu) 
{

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;



	if (!(vgpu_vreg(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))

	if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))

		return 0;



	if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
@@ -74,7 +74,7 @@ int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) 
	if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES))

		return -EINVAL;



	if (vgpu_vreg(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)

	if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)

		return 1;



	if (edp_pipe_is_enabled(vgpu) &&
@@ -169,103 +169,105 @@ static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = { 
static void emulate_monitor_status_change(struct intel_vgpu *vgpu)

{

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |

	vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |

			SDE_PORTC_HOTPLUG_CPT |

			SDE_PORTD_HOTPLUG_CPT);



	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {

		vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |

		vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |

				SDE_PORTE_HOTPLUG_SPT);

		vgpu_vreg(vgpu, SKL_FUSE_STATUS) |=

		vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=

				SKL_FUSE_DOWNLOAD_STATUS |

				SKL_FUSE_PG_DIST_STATUS(SKL_PG0) |

				SKL_FUSE_PG_DIST_STATUS(SKL_PG1) |

				SKL_FUSE_PG_DIST_STATUS(SKL_PG2);

		vgpu_vreg(vgpu, LCPLL1_CTL) |=

		vgpu_vreg_t(vgpu, LCPLL1_CTL) |=

				LCPLL_PLL_ENABLE |

				LCPLL_PLL_LOCK;

		vgpu_vreg(vgpu, LCPLL2_CTL) |= LCPLL_PLL_ENABLE;

		vgpu_vreg_t(vgpu, LCPLL2_CTL) |= LCPLL_PLL_ENABLE;



	}



	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {

		vgpu_vreg(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;

		vgpu_vreg(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=

		vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;

		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=

			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |

			TRANS_DDI_PORT_MASK);

		vgpu_vreg(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=

		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=

			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |

			(PORT_B << TRANS_DDI_PORT_SHIFT) |

			TRANS_DDI_FUNC_ENABLE);

		if (IS_BROADWELL(dev_priv)) {

			vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_B)) &=

			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=

				~PORT_CLK_SEL_MASK;

			vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_B)) |=

			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=

				PORT_CLK_SEL_LCPLL_810;

		}

		vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;

		vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;

		vgpu_vreg(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;

		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;

		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;

		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;

	}



	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {

		vgpu_vreg(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;

		vgpu_vreg(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=

		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;

		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=

			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |

			TRANS_DDI_PORT_MASK);

		vgpu_vreg(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=

		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=

			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |

			(PORT_C << TRANS_DDI_PORT_SHIFT) |

			TRANS_DDI_FUNC_ENABLE);

		if (IS_BROADWELL(dev_priv)) {

			vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_C)) &=

			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=

				~PORT_CLK_SEL_MASK;

			vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_C)) |=

			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=

				PORT_CLK_SEL_LCPLL_810;

		}

		vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;

		vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;

		vgpu_vreg(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;

		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;

		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;

		vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;

	}



	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {

		vgpu_vreg(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;

		vgpu_vreg(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=

		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;

		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=

			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |

			TRANS_DDI_PORT_MASK);

		vgpu_vreg(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=

		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=

			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |

			(PORT_D << TRANS_DDI_PORT_SHIFT) |

			TRANS_DDI_FUNC_ENABLE);

		if (IS_BROADWELL(dev_priv)) {

			vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_D)) &=

			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=

				~PORT_CLK_SEL_MASK;

			vgpu_vreg(vgpu, PORT_CLK_SEL(PORT_D)) |=

			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=

				PORT_CLK_SEL_LCPLL_810;

		}

		vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;

		vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;

		vgpu_vreg(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;

		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;

		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;

		vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;

	}



	if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&

			intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {

		vgpu_vreg(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;

		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;

	}



	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {

		if (IS_BROADWELL(dev_priv))

			vgpu_vreg(vgpu, GEN8_DE_PORT_ISR) |=

			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=

				GEN8_PORT_DP_A_HOTPLUG;

		else

			vgpu_vreg(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;

			vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;



		vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;

		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;

	}



	/* Clear host CRT status, so guest couldn't detect this host CRT. */

	if (IS_BROADWELL(dev_priv))

		vgpu_vreg(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;

		vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;



	vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;

}



static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
@@ -282,7 +284,6 @@ static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num) 
static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,

				    int type, unsigned int resolution)

{

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);



	if (WARN_ON(resolution >= GVT_EDID_NUM))
@@ -308,7 +309,7 @@ static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num, 
	port->type = type;



	emulate_monitor_status_change(vgpu);

	vgpu_vreg(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;



	return 0;

}
@@ -368,12 +369,12 @@ static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) 
		if (!pipe_is_enabled(vgpu, pipe))

			continue;



		vgpu_vreg(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;

		vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;

		intel_vgpu_trigger_virtual_event(vgpu, event);

	}



	if (pipe_is_enabled(vgpu, pipe)) {

		vgpu_vreg(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;

		vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;

		intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);

	}

}

drivers/gpu/drm/i915/gvt/edid.c

+11 −11
Original line number Diff line number Diff line
@@ -95,9 +95,9 @@ static inline int get_port_from_gmbus0(u32 gmbus0) 


static void reset_gmbus_controller(struct intel_vgpu *vgpu)

{

	vgpu_vreg(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY;

	vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY;

	if (!vgpu->display.i2c_edid.edid_available)

		vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;

		vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;

	vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;

}
@@ -123,16 +123,16 @@ static int gmbus0_mmio_write(struct intel_vgpu *vgpu, 
	vgpu->display.i2c_edid.state = I2C_GMBUS;

	vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;



	vgpu_vreg(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;

	vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE;

	vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;

	vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE;



	if (intel_vgpu_has_monitor_on_port(vgpu, port) &&

			!intel_vgpu_port_is_dp(vgpu, port)) {

		vgpu->display.i2c_edid.port = port;

		vgpu->display.i2c_edid.edid_available = true;

		vgpu_vreg(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER;

		vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER;

	} else

		vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;

		vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;

	return 0;

}
@@ -159,8 +159,8 @@ static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 
		 * 2) HW_RDY bit asserted

		 */

		if (wvalue & GMBUS_SW_CLR_INT) {

			vgpu_vreg(vgpu, PCH_GMBUS2) &= ~GMBUS_INT;

			vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY;

			vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_INT;

			vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY;

		}



		/* For virtualization, we suppose that HW is always ready,
@@ -208,7 +208,7 @@ static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 
				 * visible in gmbus interface)

				 */

				i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;

				vgpu_vreg(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;

				vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;

			}

			break;

		case NIDX_NS_W:
@@ -220,7 +220,7 @@ static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, 
			 * START (-->INDEX) -->DATA

			 */

			i2c_edid->gmbus.phase = GMBUS_DATA_PHASE;

			vgpu_vreg(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE;

			vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE;

			break;

		default:

			gvt_vgpu_err("Unknown/reserved GMBUS cycle detected!\n");
@@ -256,7 +256,7 @@ static int gmbus3_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, 
	u32 reg_data = 0;



	/* Data can only be recevied if previous settings correct */

	if (vgpu_vreg(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) {

	if (vgpu_vreg_t(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) {

		if (byte_left <= 0) {

			memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);

			return 0;

drivers/gpu/drm/i915/gvt/fb_decoder.c

+15 −15
Original line number Diff line number Diff line
@@ -147,7 +147,7 @@ static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe, 
{

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;



	u32 stride_reg = vgpu_vreg(vgpu, DSPSTRIDE(pipe)) & stride_mask;

	u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(pipe)) & stride_mask;

	u32 stride = stride_reg;



	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
@@ -209,7 +209,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, 
	if (pipe >= I915_MAX_PIPES)

		return -ENODEV;



	val = vgpu_vreg(vgpu, DSPCNTR(pipe));

	val = vgpu_vreg_t(vgpu, DSPCNTR(pipe));

	plane->enabled = !!(val & DISPLAY_PLANE_ENABLE);

	if (!plane->enabled)

		return -ENODEV;
@@ -244,7 +244,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, 


	plane->hw_format = fmt;



	plane->base = vgpu_vreg(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK;

	plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK;

	if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) {

		gvt_vgpu_err("invalid gma address: %lx\n",

			     (unsigned long)plane->base);
@@ -263,14 +263,14 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, 
			(_PRI_PLANE_STRIDE_MASK >> 6) :

				_PRI_PLANE_STRIDE_MASK, plane->bpp);



	plane->width = (vgpu_vreg(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >>

	plane->width = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >>

		_PIPE_H_SRCSZ_SHIFT;

	plane->width += 1;

	plane->height = (vgpu_vreg(vgpu, PIPESRC(pipe)) &

	plane->height = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) &

			_PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;

	plane->height += 1;	/* raw height is one minus the real value */



	val = vgpu_vreg(vgpu, DSPTILEOFF(pipe));

	val = vgpu_vreg_t(vgpu, DSPTILEOFF(pipe));

	plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >>

		_PRI_PLANE_X_OFF_SHIFT;

	plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >>
@@ -344,7 +344,7 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu, 
	if (pipe >= I915_MAX_PIPES)

		return -ENODEV;



	val = vgpu_vreg(vgpu, CURCNTR(pipe));

	val = vgpu_vreg_t(vgpu, CURCNTR(pipe));

	mode = val & CURSOR_MODE;

	plane->enabled = (mode != CURSOR_MODE_DISABLE);

	if (!plane->enabled)
@@ -370,7 +370,7 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu, 
		gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n",

			alpha_plane, alpha_force);



	plane->base = vgpu_vreg(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK;

	plane->base = vgpu_vreg_t(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK;

	if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) {

		gvt_vgpu_err("invalid gma address: %lx\n",

			     (unsigned long)plane->base);
@@ -384,7 +384,7 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu, 
		return  -EINVAL;

	}



	val = vgpu_vreg(vgpu, CURPOS(pipe));

	val = vgpu_vreg_t(vgpu, CURPOS(pipe));

	plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT;

	plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT;

	plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT;
@@ -424,7 +424,7 @@ int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu, 
	if (pipe >= I915_MAX_PIPES)

		return -ENODEV;



	val = vgpu_vreg(vgpu, SPRCTL(pipe));

	val = vgpu_vreg_t(vgpu, SPRCTL(pipe));

	plane->enabled = !!(val & SPRITE_ENABLE);

	if (!plane->enabled)

		return -ENODEV;
@@ -475,7 +475,7 @@ int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu, 


	plane->drm_format = drm_format;



	plane->base = vgpu_vreg(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK;

	plane->base = vgpu_vreg_t(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK;

	if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0)) {

		gvt_vgpu_err("invalid gma address: %lx\n",

			     (unsigned long)plane->base);
@@ -489,10 +489,10 @@ int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu, 
		return  -EINVAL;

	}



	plane->stride = vgpu_vreg(vgpu, SPRSTRIDE(pipe)) &

	plane->stride = vgpu_vreg_t(vgpu, SPRSTRIDE(pipe)) &

				_SPRITE_STRIDE_MASK;



	val = vgpu_vreg(vgpu, SPRSIZE(pipe));

	val = vgpu_vreg_t(vgpu, SPRSIZE(pipe));

	plane->height = (val & _SPRITE_SIZE_HEIGHT_MASK) >>

		_SPRITE_SIZE_HEIGHT_SHIFT;

	plane->width = (val & _SPRITE_SIZE_WIDTH_MASK) >>
@@ -500,11 +500,11 @@ int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu, 
	plane->height += 1;	/* raw height is one minus the real value */

	plane->width += 1;	/* raw width is one minus the real value */



	val = vgpu_vreg(vgpu, SPRPOS(pipe));

	val = vgpu_vreg_t(vgpu, SPRPOS(pipe));

	plane->x_pos = (val & _SPRITE_POS_X_MASK) >> _SPRITE_POS_X_SHIFT;

	plane->y_pos = (val & _SPRITE_POS_Y_MASK) >> _SPRITE_POS_Y_SHIFT;



	val = vgpu_vreg(vgpu, SPROFFSET(pipe));

	val = vgpu_vreg_t(vgpu, SPROFFSET(pipe));

	plane->x_offset = (val & _SPRITE_OFFSET_START_X_MASK) >>

			   _SPRITE_OFFSET_START_X_SHIFT;

	plane->y_offset = (val & _SPRITE_OFFSET_START_Y_MASK) >>

drivers/gpu/drm/i915/gvt/gtt.c

+35 −2
Original line number Diff line number Diff line
@@ -1968,6 +1968,39 @@ int intel_vgpu_emulate_gtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 
	return ret;

}



int intel_vgpu_write_protect_handler(struct intel_vgpu *vgpu, u64 pa,

				     void *p_data, unsigned int bytes)

{

	struct intel_gvt *gvt = vgpu->gvt;

	int ret = 0;



	if (atomic_read(&vgpu->gtt.n_tracked_guest_page)) {

		struct intel_vgpu_page_track *t;



		mutex_lock(&gvt->lock);



		t = intel_vgpu_find_tracked_page(vgpu, pa >> PAGE_SHIFT);

		if (t) {

			if (unlikely(vgpu->failsafe)) {

				/* remove write protection to prevent furture traps */

				intel_vgpu_clean_page_track(vgpu, t);

			} else {

				ret = t->handler(t, pa, p_data, bytes);

				if (ret) {

					gvt_err("guest page write error %d, "

						"gfn 0x%lx, pa 0x%llx, "

						"var 0x%x, len %d\n",

						ret, t->gfn, pa,

						*(u32 *)p_data, bytes);

				}

			}

		}

		mutex_unlock(&gvt->lock);

	}

	return ret;

}





static int alloc_scratch_pages(struct intel_vgpu *vgpu,

		intel_gvt_gtt_type_t type)

{
@@ -2244,7 +2277,7 @@ struct intel_vgpu_mm *intel_vgpu_find_ppgtt_mm(struct intel_vgpu *vgpu, 
int intel_vgpu_g2v_create_ppgtt_mm(struct intel_vgpu *vgpu,

		int page_table_level)

{

	u64 *pdp = (u64 *)&vgpu_vreg64(vgpu, vgtif_reg(pdp[0]));

	u64 *pdp = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0]));

	struct intel_vgpu_mm *mm;



	if (WARN_ON((page_table_level != 4) && (page_table_level != 3)))
@@ -2279,7 +2312,7 @@ int intel_vgpu_g2v_create_ppgtt_mm(struct intel_vgpu *vgpu, 
int intel_vgpu_g2v_destroy_ppgtt_mm(struct intel_vgpu *vgpu,

		int page_table_level)

{

	u64 *pdp = (u64 *)&vgpu_vreg64(vgpu, vgtif_reg(pdp[0]));

	u64 *pdp = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0]));

	struct intel_vgpu_mm *mm;



	if (WARN_ON((page_table_level != 4) && (page_table_level != 3)))

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