nds32: support hardware prefetcher (e2f3f8b4) · Commits · 戴 / test

arch/nds32/Kconfig.cpu

+7 −0

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		@@ -177,6 +177,13 @@ config CACHE_L2
		Say Y here to enable L2 cache if your SoC are integrated with L2CC.
		If unsure, say N.

		config HW_PRE
		bool "Enable hardware prefetcher"
		default y
		help
		Say Y here to enable hardware prefetcher feature.
		Only when CPU_VER.REV >= 0x09 can support.

		menu "Memory configuration"

		choice

+6 −0

Original line number	Diff line number	Diff line
		@@ -740,14 +740,20 @@
		#define N13MISC_CTL_offRTP 1 /* Disable Return Target Predictor */
		#define N13MISC_CTL_offPTEPF 2 /* Disable HPTWK L2 PTE pefetch */
		#define N13MISC_CTL_offSP_SHADOW_EN 4 /* Enable shadow stack pointers */
		#define MISC_CTL_offHWPRE 11 /* Enable HardWare PREFETCH */
		/* bit 6, 9:31 reserved */

		#define N13MISC_CTL_makBTB ( 0x1 << N13MISC_CTL_offBTB )
		#define N13MISC_CTL_makRTP ( 0x1 << N13MISC_CTL_offRTP )
		#define N13MISC_CTL_makPTEPF ( 0x1 << N13MISC_CTL_offPTEPF )
		#define N13MISC_CTL_makSP_SHADOW_EN ( 0x1 << N13MISC_CTL_offSP_SHADOW_EN )
		#define MISC_CTL_makHWPRE_EN ( 0x1 << MISC_CTL_offHWPRE )

		#ifdef CONFIG_HW_PRE
		#define MISC_init (N13MISC_CTL_makBTB\|N13MISC_CTL_makRTP\|N13MISC_CTL_makSP_SHADOW_EN\|MISC_CTL_makHWPRE_EN)
		#else
		#define MISC_init (N13MISC_CTL_makBTB\|N13MISC_CTL_makRTP\|N13MISC_CTL_makSP_SHADOW_EN)
		#endif

		/******************************************************************************
		* PRUSR_ACC_CTL (Privileged Resource User Access Control Registers)

+1 −1

Original line number	Diff line number	Diff line
		@@ -151,7 +151,7 @@ _tlb:
		#endif
		mtsr $r3, $TLB_MISC

		mfsr $r0, $MISC_CTL ! Enable BTB and RTP and shadow sp
		mfsr $r0, $MISC_CTL ! Enable BTB, RTP, shadow sp, and HW_PRE
		ori $r0, $r0, #MISC_init
		mtsr $r0, $MISC_CTL

+7 −0

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		@@ -39,6 +39,7 @@
		#define HWCAP_FPU_DP 0x040000
		#define HWCAP_V2 0x080000
		#define HWCAP_DX_REGS 0x100000
		#define HWCAP_HWPRE 0x200000

		unsigned long cpu_id, cpu_rev, cpu_cfgid;
		bool has_fpu = false;
		@@ -75,6 +76,7 @@ static const char *hwcap_str[] = {
		"fpu_dp",
		"v2",
		"dx_regs",
		"hw_pre",
		NULL,
		};

		@@ -221,6 +223,11 @@ static void __init setup_cpuinfo(void)
		if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskL2C)
		elf_hwcap \|= HWCAP_L2C;

		#ifdef CONFIG_HW_PRE
		if (__nds32__mfsr(NDS32_SR_MISC_CTL) & MISC_CTL_makHWPRE_EN)
		elf_hwcap \|= HWCAP_HWPRE;
		#endif

		tmp = __nds32__mfsr(NDS32_SR_CACHE_CTL);
		if (!IS_ENABLED(CONFIG_CPU_DCACHE_DISABLE))
		tmp \|= CACHE_CTL_mskDC_EN;