Merge branch 'pm-cpufreq' (e27f84e1) · Commits · 戴 / test

Documentation/devicetree/bindings/opp/kryo-cpufreq.txt

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		Qualcomm Technologies, Inc. KRYO CPUFreq and OPP bindings
		===================================

		In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996
		that have KRYO processors, the CPU ferequencies subset and voltage value
		of each OPP varies based on the silicon variant in use.
		Qualcomm Technologies, Inc. Process Voltage Scaling Tables
		defines the voltage and frequency value based on the msm-id in SMEM
		and speedbin blown in the efuse combination.
		The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
		to provide the OPP framework with required information (existing HW bitmap).
		This is used to determine the voltage and frequency value for each OPP of
		operating-points-v2 table when it is parsed by the OPP framework.

		Required properties:
		--------------------
		In 'cpus' nodes:
		- operating-points-v2: Phandle to the operating-points-v2 table to use.

		In 'operating-points-v2' table:
		- compatible: Should be
		- 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.
		- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
		efuse registers that has information about the
		speedbin that is used to select the right frequency/voltage
		value pair.
		Please refer the for nvmem-cells
		bindings Documentation/devicetree/bindings/nvmem/nvmem.txt
		and also examples below.

		In every OPP node:
		- opp-supported-hw: A single 32 bit bitmap value, representing compatible HW.
		Bitmap:
		0: MSM8996 V3, speedbin 0
		1: MSM8996 V3, speedbin 1
		2: MSM8996 V3, speedbin 2
		3: unused
		4: MSM8996 SG, speedbin 0
		5: MSM8996 SG, speedbin 1
		6: MSM8996 SG, speedbin 2
		7-31: unused

		Example 1:
		---------

		cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
		device_type = "cpu";
		compatible = "qcom,kryo";
		reg = <0x0 0x0>;
		enable-method = "psci";
		clocks = <&kryocc 0>;
		cpu-supply = <&pm8994_s11_saw>;
		operating-points-v2 = <&cluster0_opp>;
		#cooling-cells = <2>;
		next-level-cache = <&L2_0>;
		L2_0: l2-cache {
		compatible = "cache";
		cache-level = <2>;
		};
		};

		CPU1: cpu@1 {
		device_type = "cpu";
		compatible = "qcom,kryo";
		reg = <0x0 0x1>;
		enable-method = "psci";
		clocks = <&kryocc 0>;
		cpu-supply = <&pm8994_s11_saw>;
		operating-points-v2 = <&cluster0_opp>;
		#cooling-cells = <2>;
		next-level-cache = <&L2_0>;
		};

		CPU2: cpu@100 {
		device_type = "cpu";
		compatible = "qcom,kryo";
		reg = <0x0 0x100>;
		enable-method = "psci";
		clocks = <&kryocc 1>;
		cpu-supply = <&pm8994_s11_saw>;
		operating-points-v2 = <&cluster1_opp>;
		#cooling-cells = <2>;
		next-level-cache = <&L2_1>;
		L2_1: l2-cache {
		compatible = "cache";
		cache-level = <2>;
		};
		};

		CPU3: cpu@101 {
		device_type = "cpu";
		compatible = "qcom,kryo";
		reg = <0x0 0x101>;
		enable-method = "psci";
		clocks = <&kryocc 1>;
		cpu-supply = <&pm8994_s11_saw>;
		operating-points-v2 = <&cluster1_opp>;
		#cooling-cells = <2>;
		next-level-cache = <&L2_1>;
		};

		cpu-map {
		cluster0 {
		core0 {
		cpu = <&CPU0>;
		};

		core1 {
		cpu = <&CPU1>;
		};
		};

		cluster1 {
		core0 {
		cpu = <&CPU2>;
		};

		core1 {
		cpu = <&CPU3>;
		};
		};
		};
		};

		cluster0_opp: opp_table0 {
		compatible = "operating-points-v2-kryo-cpu";
		nvmem-cells = <&speedbin_efuse>;
		opp-shared;

		opp-307200000 {
		opp-hz = /bits/ 64 <307200000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x77>;
		clock-latency-ns = <200000>;
		};
		opp-384000000 {
		opp-hz = /bits/ 64 <384000000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-422400000 {
		opp-hz = /bits/ 64 <422400000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-460800000 {
		opp-hz = /bits/ 64 <460800000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-480000000 {
		opp-hz = /bits/ 64 <480000000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-537600000 {
		opp-hz = /bits/ 64 <537600000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-556800000 {
		opp-hz = /bits/ 64 <556800000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-614400000 {
		opp-hz = /bits/ 64 <614400000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-652800000 {
		opp-hz = /bits/ 64 <652800000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-691200000 {
		opp-hz = /bits/ 64 <691200000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-729600000 {
		opp-hz = /bits/ 64 <729600000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-768000000 {
		opp-hz = /bits/ 64 <768000000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-844800000 {
		opp-hz = /bits/ 64 <844800000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x77>;
		clock-latency-ns = <200000>;
		};
		opp-902400000 {
		opp-hz = /bits/ 64 <902400000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-960000000 {
		opp-hz = /bits/ 64 <960000000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-979200000 {
		opp-hz = /bits/ 64 <979200000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-1036800000 {
		opp-hz = /bits/ 64 <1036800000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-1056000000 {
		opp-hz = /bits/ 64 <1056000000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-1113600000 {
		opp-hz = /bits/ 64 <1113600000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-1132800000 {
		opp-hz = /bits/ 64 <1132800000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-1190400000 {
		opp-hz = /bits/ 64 <1190400000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-1209600000 {
		opp-hz = /bits/ 64 <1209600000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-1228800000 {
		opp-hz = /bits/ 64 <1228800000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-1286400000 {
		opp-hz = /bits/ 64 <1286400000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-1324800000 {
		opp-hz = /bits/ 64 <1324800000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x5>;
		clock-latency-ns = <200000>;
		};
		opp-1363200000 {
		opp-hz = /bits/ 64 <1363200000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x72>;
		clock-latency-ns = <200000>;
		};
		opp-1401600000 {
		opp-hz = /bits/ 64 <1401600000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x5>;
		clock-latency-ns = <200000>;
		};
		opp-1440000000 {
		opp-hz = /bits/ 64 <1440000000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-1478400000 {
		opp-hz = /bits/ 64 <1478400000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x1>;
		clock-latency-ns = <200000>;
		};
		opp-1497600000 {
		opp-hz = /bits/ 64 <1497600000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x4>;
		clock-latency-ns = <200000>;
		};
		opp-1516800000 {
		opp-hz = /bits/ 64 <1516800000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-1593600000 {
		opp-hz = /bits/ 64 <1593600000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x71>;
		clock-latency-ns = <200000>;
		};
		opp-1996800000 {
		opp-hz = /bits/ 64 <1996800000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x20>;
		clock-latency-ns = <200000>;
		};
		opp-2188800000 {
		opp-hz = /bits/ 64 <2188800000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x10>;
		clock-latency-ns = <200000>;
		};
		};

		cluster1_opp: opp_table1 {
		compatible = "operating-points-v2-kryo-cpu";
		nvmem-cells = <&speedbin_efuse>;
		opp-shared;

		opp-307200000 {
		opp-hz = /bits/ 64 <307200000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x77>;
		clock-latency-ns = <200000>;
		};
		opp-384000000 {
		opp-hz = /bits/ 64 <384000000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-403200000 {
		opp-hz = /bits/ 64 <403200000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-460800000 {
		opp-hz = /bits/ 64 <460800000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-480000000 {
		opp-hz = /bits/ 64 <480000000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-537600000 {
		opp-hz = /bits/ 64 <537600000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-556800000 {
		opp-hz = /bits/ 64 <556800000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-614400000 {
		opp-hz = /bits/ 64 <614400000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-652800000 {
		opp-hz = /bits/ 64 <652800000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-691200000 {
		opp-hz = /bits/ 64 <691200000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-729600000 {
		opp-hz = /bits/ 64 <729600000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-748800000 {
		opp-hz = /bits/ 64 <748800000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-806400000 {
		opp-hz = /bits/ 64 <806400000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-825600000 {
		opp-hz = /bits/ 64 <825600000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-883200000 {
		opp-hz = /bits/ 64 <883200000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-902400000 {
		opp-hz = /bits/ 64 <902400000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-940800000 {
		opp-hz = /bits/ 64 <940800000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-979200000 {
		opp-hz = /bits/ 64 <979200000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-1036800000 {
		opp-hz = /bits/ 64 <1036800000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-1056000000 {
		opp-hz = /bits/ 64 <1056000000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-1113600000 {
		opp-hz = /bits/ 64 <1113600000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-1132800000 {
		opp-hz = /bits/ 64 <1132800000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-1190400000 {
		opp-hz = /bits/ 64 <1190400000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-1209600000 {
		opp-hz = /bits/ 64 <1209600000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-1248000000 {
		opp-hz = /bits/ 64 <1248000000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-1286400000 {
		opp-hz = /bits/ 64 <1286400000>;
		opp-microvolt = <905000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-1324800000 {
		opp-hz = /bits/ 64 <1324800000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-1363200000 {
		opp-hz = /bits/ 64 <1363200000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-1401600000 {
		opp-hz = /bits/ 64 <1401600000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-1440000000 {
		opp-hz = /bits/ 64 <1440000000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-1478400000 {
		opp-hz = /bits/ 64 <1478400000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-1516800000 {
		opp-hz = /bits/ 64 <1516800000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-1555200000 {
		opp-hz = /bits/ 64 <1555200000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-1593600000 {
		opp-hz = /bits/ 64 <1593600000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-1632000000 {
		opp-hz = /bits/ 64 <1632000000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-1670400000 {
		opp-hz = /bits/ 64 <1670400000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-1708800000 {
		opp-hz = /bits/ 64 <1708800000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-1747200000 {
		opp-hz = /bits/ 64 <1747200000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x70>;
		clock-latency-ns = <200000>;
		};
		opp-1785600000 {
		opp-hz = /bits/ 64 <1785600000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x7>;
		clock-latency-ns = <200000>;
		};
		opp-1804800000 {
		opp-hz = /bits/ 64 <1804800000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x6>;
		clock-latency-ns = <200000>;
		};
		opp-1824000000 {
		opp-hz = /bits/ 64 <1824000000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x71>;
		clock-latency-ns = <200000>;
		};
		opp-1900800000 {
		opp-hz = /bits/ 64 <1900800000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x74>;
		clock-latency-ns = <200000>;
		};
		opp-1920000000 {
		opp-hz = /bits/ 64 <1920000000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x1>;
		clock-latency-ns = <200000>;
		};
		opp-1977600000 {
		opp-hz = /bits/ 64 <1977600000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x30>;
		clock-latency-ns = <200000>;
		};
		opp-1996800000 {
		opp-hz = /bits/ 64 <1996800000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x1>;
		clock-latency-ns = <200000>;
		};
		opp-2054400000 {
		opp-hz = /bits/ 64 <2054400000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x30>;
		clock-latency-ns = <200000>;
		};
		opp-2073600000 {
		opp-hz = /bits/ 64 <2073600000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x1>;
		clock-latency-ns = <200000>;
		};
		opp-2150400000 {
		opp-hz = /bits/ 64 <2150400000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x31>;
		clock-latency-ns = <200000>;
		};
		opp-2246400000 {
		opp-hz = /bits/ 64 <2246400000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x10>;
		clock-latency-ns = <200000>;
		};
		opp-2342400000 {
		opp-hz = /bits/ 64 <2342400000>;
		opp-microvolt = <1140000 905000 1140000>;
		opp-supported-hw = <0x10>;
		clock-latency-ns = <200000>;
		};
		};

		....

		reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		....
		smem_mem: smem-mem@86000000 {
		reg = <0x0 0x86000000 0x0 0x200000>;
		no-map;
		};
		....
		};

		smem {
		compatible = "qcom,smem";
		memory-region = <&smem_mem>;
		hwlocks = <&tcsr_mutex 3>;
		};

		soc {
		....
		qfprom: qfprom@74000 {
		compatible = "qcom,qfprom";
		reg = <0x00074000 0x8ff>;
		#address-cells = <1>;
		#size-cells = <1>;
		....
		speedbin_efuse: speedbin@133 {
		reg = <0x133 0x1>;
		bits = <5 3>;
		};
		};
		};

MAINTAINERS

+7 −0

Original line number	Diff line number	Diff line
		@@ -11654,6 +11654,13 @@ F: Documentation/devicetree/bindings/media/qcom,camss.txt
		F: Documentation/media/v4l-drivers/qcom_camss.rst
		F: drivers/media/platform/qcom/camss-8x16/

		QUALCOMM CPUFREQ DRIVER MSM8996/APQ8096
		M: Ilia Lin <ilia.lin@gmail.com>
		L: linux-pm@vger.kernel.org
		S: Maintained
		F: Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
		F: drivers/cpufreq/qcom-cpufreq-kryo.c

		QUALCOMM EMAC GIGABIT ETHERNET DRIVER
		M: Timur Tabi <timur@codeaurora.org>
		L: netdev@vger.kernel.org

drivers/cpufreq/Kconfig.arm

+12 −1

Original line number	Diff line number	Diff line
		@@ -124,6 +124,17 @@ config ARM_OMAP2PLUS_CPUFREQ
		depends on ARCH_OMAP2PLUS
		default ARCH_OMAP2PLUS

		config ARM_QCOM_CPUFREQ_KRYO
		bool "Qualcomm Kryo based CPUFreq"
		depends on ARM64
		depends on QCOM_QFPROM
		depends on QCOM_SMEM
		select PM_OPP
		help
		This adds the CPUFreq driver for Qualcomm Kryo SoC based boards.

		If in doubt, say N.

		config ARM_S3C_CPUFREQ
		bool
		help
		@@ -264,7 +275,7 @@ config ARM_TANGO_CPUFREQ
		default y

		config ARM_TEGRA20_CPUFREQ
		bool "Tegra20 CPUFreq support"
		tristate "Tegra20 CPUFreq support"
		depends on ARCH_TEGRA
		default y
		help

drivers/cpufreq/Makefile

+1 −0

Original line number	Diff line number	Diff line
		@@ -65,6 +65,7 @@ obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o
		obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o
		obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o
		obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o
		obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRYO) += qcom-cpufreq-kryo.o
		obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o
		obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o
		obj-$(CONFIG_ARM_S3C2416_CPUFREQ) += s3c2416-cpufreq.o

drivers/cpufreq/armada-37xx-cpufreq.c

+87 −13

Original line number	Diff line number	Diff line
		@@ -23,6 +23,8 @@
		#include <linux/regmap.h>
		#include <linux/slab.h>

		#include "cpufreq-dt.h"

		/* Power management in North Bridge register set */
		#define ARMADA_37XX_NB_L0L1 0x18
		#define ARMADA_37XX_NB_L2L3 0x1C
		@@ -56,6 +58,16 @@
		*/
		#define LOAD_LEVEL_NR 4

		struct armada37xx_cpufreq_state {
		struct regmap *regmap;
		u32 nb_l0l1;
		u32 nb_l2l3;
		u32 nb_dyn_mod;
		u32 nb_cpu_load;
		};

		static struct armada37xx_cpufreq_state *armada37xx_cpufreq_state;

		struct armada_37xx_dvfs {
		u32 cpu_freq_max;
		u8 divider[LOAD_LEVEL_NR];
		@@ -136,7 +148,7 @@ static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
		clk_set_parent(clk, parent);
		}

		static void __init armada37xx_cpufreq_disable_dvfs(struct regmap *base)
		static void armada37xx_cpufreq_disable_dvfs(struct regmap *base)
		{
		unsigned int reg = ARMADA_37XX_NB_DYN_MOD,
		mask = ARMADA_37XX_NB_DFS_EN;
		@@ -162,10 +174,47 @@ static void __init armada37xx_cpufreq_enable_dvfs(struct regmap *base)
		regmap_update_bits(base, reg, mask, mask);
		}

		static int armada37xx_cpufreq_suspend(struct cpufreq_policy *policy)
		{
		struct armada37xx_cpufreq_state *state = armada37xx_cpufreq_state;

		regmap_read(state->regmap, ARMADA_37XX_NB_L0L1, &state->nb_l0l1);
		regmap_read(state->regmap, ARMADA_37XX_NB_L2L3, &state->nb_l2l3);
		regmap_read(state->regmap, ARMADA_37XX_NB_CPU_LOAD,
		&state->nb_cpu_load);
		regmap_read(state->regmap, ARMADA_37XX_NB_DYN_MOD, &state->nb_dyn_mod);

		return 0;
		}

		static int armada37xx_cpufreq_resume(struct cpufreq_policy *policy)
		{
		struct armada37xx_cpufreq_state *state = armada37xx_cpufreq_state;

		/* Ensure DVFS is disabled otherwise the following registers are RO */
		armada37xx_cpufreq_disable_dvfs(state->regmap);

		regmap_write(state->regmap, ARMADA_37XX_NB_L0L1, state->nb_l0l1);
		regmap_write(state->regmap, ARMADA_37XX_NB_L2L3, state->nb_l2l3);
		regmap_write(state->regmap, ARMADA_37XX_NB_CPU_LOAD,
		state->nb_cpu_load);

		/*
		* NB_DYN_MOD register is the one that actually enable back DVFS if it
		* was enabled before the suspend operation. This must be done last
		* otherwise other registers are not writable.
		*/
		regmap_write(state->regmap, ARMADA_37XX_NB_DYN_MOD, state->nb_dyn_mod);

		return 0;
		}

		static int __init armada37xx_cpufreq_driver_init(void)
		{
		struct cpufreq_dt_platform_data pdata;
		struct armada_37xx_dvfs *dvfs;
		struct platform_device *pdev;
		unsigned long freq;
		unsigned int cur_frequency;
		struct regmap *nb_pm_base;
		struct device *cpu_dev;
		@@ -207,33 +256,58 @@ static int __init armada37xx_cpufreq_driver_init(void)
		}

		dvfs = armada_37xx_cpu_freq_info_get(cur_frequency);
		if (!dvfs)
		if (!dvfs) {
		clk_put(clk);
		return -EINVAL;
		}

		armada37xx_cpufreq_state = kmalloc(sizeof(*armada37xx_cpufreq_state),
		GFP_KERNEL);
		if (!armada37xx_cpufreq_state) {
		clk_put(clk);
		return -ENOMEM;
		}

		armada37xx_cpufreq_state->regmap = nb_pm_base;

		armada37xx_cpufreq_dvfs_setup(nb_pm_base, clk, dvfs->divider);
		clk_put(clk);

		for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
		load_lvl++) {
		unsigned long freq = cur_frequency / dvfs->divider[load_lvl];
		freq = cur_frequency / dvfs->divider[load_lvl];

		ret = dev_pm_opp_add(cpu_dev, freq, 0);
		if (ret) {
		if (ret)
		goto remove_opp;
		}

		/* Now that everything is setup, enable the DVFS at hardware level */
		armada37xx_cpufreq_enable_dvfs(nb_pm_base);

		pdata.suspend = armada37xx_cpufreq_suspend;
		pdata.resume = armada37xx_cpufreq_resume;

		pdev = platform_device_register_data(NULL, "cpufreq-dt", -1, &pdata,
		sizeof(pdata));
		ret = PTR_ERR_OR_ZERO(pdev);
		if (ret)
		goto disable_dvfs;

		return 0;

		disable_dvfs:
		armada37xx_cpufreq_disable_dvfs(nb_pm_base);
		remove_opp:
		/* clean-up the already added opp before leaving */
		while (load_lvl-- > ARMADA_37XX_DVFS_LOAD_0) {
		freq = cur_frequency / dvfs->divider[load_lvl];
		dev_pm_opp_remove(cpu_dev, freq);
		}
		return ret;
		}
		}

		/* Now that everything is setup, enable the DVFS at hardware level */
		armada37xx_cpufreq_enable_dvfs(nb_pm_base);
		kfree(armada37xx_cpufreq_state);

		pdev = platform_device_register_simple("cpufreq-dt", -1, NULL, 0);

		return PTR_ERR_OR_ZERO(pdev);
		return ret;
		}
		/* late_initcall, to guarantee the driver is loaded after A37xx clock driver */
		late_initcall(armada37xx_cpufreq_driver_init);

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