powerpc/xive: Remove xive_kexec_teardown_cpu() (e27e0a94) · Commits · 戴 / test

arch/powerpc/include/asm/xive.h

+0 −1

Original line number	Diff line number	Diff line
		@@ -87,7 +87,6 @@ extern int xive_smp_prepare_cpu(unsigned int cpu);
		extern void xive_smp_setup_cpu(void);
		extern void xive_smp_disable_cpu(void);
		extern void xive_teardown_cpu(void);
		extern void xive_kexec_teardown_cpu(int secondary);
		extern void xive_shutdown(void);
		extern void xive_flush_interrupt(void);

+1 −1

Original line number	Diff line number	Diff line
		@@ -314,7 +314,7 @@ static void pnv_kexec_cpu_down(int crash_shutdown, int secondary)
		u64 reinit_flags;

		if (xive_enabled())
		xive_kexec_teardown_cpu(secondary);
		xive_teardown_cpu();
		else
		xics_kexec_teardown_cpu(secondary);

+1 −1

Original line number	Diff line number	Diff line
		@@ -58,7 +58,7 @@ void pseries_kexec_cpu_down(int crash_shutdown, int secondary)
		}

		if (xive_enabled()) {
		xive_kexec_teardown_cpu(secondary);
		xive_teardown_cpu();

		if (!secondary)
		xive_shutdown();

+0 −22

Original line number	Diff line number	Diff line
		@@ -1408,28 +1408,6 @@ void xive_teardown_cpu(void)
		xive_cleanup_cpu_queues(cpu, xc);
		}

		void xive_kexec_teardown_cpu(int secondary)
		{
		struct xive_cpu *xc = __this_cpu_read(xive_cpu);
		unsigned int cpu = smp_processor_id();

		/* Set CPPR to 0 to disable flow of interrupts */
		xc->cppr = 0;
		out_8(xive_tima + xive_tima_offset + TM_CPPR, 0);

		/* Backend cleanup if any */
		if (xive_ops->teardown_cpu)
		xive_ops->teardown_cpu(cpu, xc);

		#ifdef CONFIG_SMP
		/* Get rid of IPI */
		xive_cleanup_cpu_ipi(cpu, xc);
		#endif

		/* Disable and free the queues */
		xive_cleanup_cpu_queues(cpu, xc);
		}

		void xive_shutdown(void)
		{
		xive_ops->shutdown();