Commit e27a73d1 authored by Emily Deng's avatar Emily Deng Committed by Alex Deucher
Browse files

drm/amdgpu/psp: Correct and refine the vmr support. (v2) 



Currently driver only psp v11 support vmr.

v2: squash in unused variable removal (Alex)

Signed-off-by: default avatarEmily Deng <Emily.Deng@amd.com>
Reviewed-by: default avatarXiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e30c50cd

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+0 −8
Original line number Diff line number Diff line
@@ -155,14 +155,6 @@ psp_cmd_submit_buf(struct psp_context *psp, 
	return ret;

}



bool psp_support_vmr_ring(struct psp_context *psp)

{

	if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045)

		return true;

	else

		return false;

}



static void psp_prep_tmr_cmd_buf(struct psp_context *psp,

				 struct psp_gfx_cmd_resp *cmd,

				 uint64_t tmr_mc, uint32_t size)

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h

+3 −2
Original line number Diff line number Diff line
@@ -89,6 +89,7 @@ struct psp_funcs 
				      struct psp_xgmi_topology_info *topology);

	int (*xgmi_set_topology_info)(struct psp_context *psp, int number_devices,

				      struct psp_xgmi_topology_info *topology);

	bool (*support_vmr_ring)(struct psp_context *psp);

};



struct psp_xgmi_context {
@@ -192,6 +193,8 @@ struct psp_xgmi_topology_info { 
		((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)

#define psp_smu_reload_quirk(psp) \

		((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)

#define psp_support_vmr_ring(psp) \

		((psp)->funcs->support_vmr_ring ? (psp)->funcs->support_vmr_ring((psp)) : false)

#define psp_mode1_reset(psp) \

		((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)

#define psp_xgmi_get_node_id(psp) \
@@ -217,8 +220,6 @@ extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; 


int psp_gpu_reset(struct amdgpu_device *adev);

int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);

bool psp_support_vmr_ring(struct psp_context *psp);



extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;



#endif

drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

+13 −5
Original line number Diff line number Diff line
@@ -291,6 +291,13 @@ static int psp_v11_0_ring_init(struct psp_context *psp, 
	return 0;

}



static bool psp_v11_0_support_vmr_ring(struct psp_context *psp)

{

	if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045)

		return true;

	return false;

}



static int psp_v11_0_ring_create(struct psp_context *psp,

				enum psp_ring_type ring_type)

{
@@ -299,7 +306,7 @@ static int psp_v11_0_ring_create(struct psp_context *psp, 
	struct psp_ring *ring = &psp->km_ring;

	struct amdgpu_device *adev = psp->adev;



	if (psp_support_vmr_ring(psp)) {

	if (psp_v11_0_support_vmr_ring(psp)) {

		/* Write low address of the ring to C2PMSG_102 */

		psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);

		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
@@ -351,7 +358,7 @@ static int psp_v11_0_ring_stop(struct psp_context *psp, 
	struct amdgpu_device *adev = psp->adev;



	/* Write the ring destroy command*/

	if (psp_support_vmr_ring(psp))

	if (psp_v11_0_support_vmr_ring(psp))

		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,

				     GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);

	else
@@ -362,7 +369,7 @@ static int psp_v11_0_ring_stop(struct psp_context *psp, 
	mdelay(20);



	/* Wait for response flag (bit 31) */

	if (psp_support_vmr_ring(psp))

	if (psp_v11_0_support_vmr_ring(psp))

		ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),

				   0x80000000, 0x80000000, false);

	else
@@ -406,7 +413,7 @@ static int psp_v11_0_cmd_submit(struct psp_context *psp, 
	uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;



	/* KM (GPCOM) prepare write pointer */

	if (psp_support_vmr_ring(psp))

	if (psp_v11_0_support_vmr_ring(psp))

		psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);

	else

		psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
@@ -438,7 +445,7 @@ static int psp_v11_0_cmd_submit(struct psp_context *psp, 


	/* Update the write Pointer in DWORDs */

	psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;

	if (psp_support_vmr_ring(psp)) {

	if (psp_v11_0_support_vmr_ring(psp)) {

		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);

		WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);

	} else
@@ -732,6 +739,7 @@ static const struct psp_funcs psp_v11_0_funcs = { 
	.xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info,

	.xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id,

	.xgmi_get_node_id = psp_v11_0_xgmi_get_node_id,

	.support_vmr_ring = psp_v11_0_support_vmr_ring,

};



void psp_v11_0_set_psp_funcs(struct psp_context *psp)

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