Commit e26a2033 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-hi3798cv200-4.17' of... 

Merge tag 'clk-hi3798cv200-4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-hisi

Pull Hi3798CV200 clock driver updates for 4.17 from Shawn Guo:

 - Add COMBPHY0 and USB2_OTG_UTMI clock support.
 - Correct the parent clock of HISTB_IR_CLK.
 - Fix unregister call sequence in hi3798cv200_clk_register() function.
 - A coding-style improvement on Hi3798CV200 driver code indent.
 - Add a HiSilicon specific phase clock type and using the type for eMMC
   clocks on Hi3798CV200.

* tag 'clk-hi3798cv200-4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  clk: hi3798cv200: add emmc sample and drive clock
  clk: hisilicon: add hisi phase clock support
  clk: hi3798cv200: add COMBPHY0 clock support
  clk: hi3798cv200: fix define indentation
  clk: hi3798cv200: add support for HISTB_USB2_OTG_UTMI_CLK
  clk: hi3798cv200: correct IR clock parent
  clk: hi3798cv200: fix unregister call sequence in error path
parents 7928b2cb d1b03995

drivers/clk/hisilicon/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 
# Hisilicon Clock specific Makefile

#



obj-y	+= clk.o clkgate-separated.o clkdivider-hi6220.o

obj-y	+= clk.o clkgate-separated.o clkdivider-hi6220.o clk-hisi-phase.o



obj-$(CONFIG_ARCH_HI3xxx)	+= clk-hi3620.o

obj-$(CONFIG_ARCH_HIP04)	+= clk-hip04.o

drivers/clk/hisilicon/clk-hisi-phase.c

0 → 100644
+121 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2017 HiSilicon Technologies Co., Ltd.

 *

 * Simple HiSilicon phase clock implementation.

 */



#include <linux/err.h>

#include <linux/io.h>

#include <linux/module.h>

#include <linux/platform_device.h>

#include <linux/slab.h>



#include "clk.h"



struct clk_hisi_phase {

	struct clk_hw	hw;

	void __iomem	*reg;

	u32		*phase_degrees;

	u32		*phase_regvals;

	u8		phase_num;

	u32		mask;

	u8		shift;

	u8		flags;

	spinlock_t	*lock;

};



#define to_clk_hisi_phase(_hw) container_of(_hw, struct clk_hisi_phase, hw)



static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase,

					u32 regval)

{

	int i;



	for (i = 0; i < phase->phase_num; i++)

		if (phase->phase_regvals[i] == regval)

			return phase->phase_degrees[i];



	return -EINVAL;

}



static int hisi_clk_get_phase(struct clk_hw *hw)

{

	struct clk_hisi_phase *phase = to_clk_hisi_phase(hw);

	u32 regval;



	regval = readl(phase->reg);

	regval = (regval & phase->mask) >> phase->shift;



	return hisi_phase_regval_to_degrees(phase, regval);

}



static int hisi_phase_degrees_to_regval(struct clk_hisi_phase *phase,

					int degrees)

{

	int i;



	for (i = 0; i < phase->phase_num; i++)

		if (phase->phase_degrees[i] == degrees)

			return phase->phase_regvals[i];



	return -EINVAL;

}



static int hisi_clk_set_phase(struct clk_hw *hw, int degrees)

{

	struct clk_hisi_phase *phase = to_clk_hisi_phase(hw);

	unsigned long flags = 0;

	int regval;

	u32 val;



	regval = hisi_phase_degrees_to_regval(phase, degrees);

	if (regval < 0)

		return regval;



	spin_lock_irqsave(phase->lock, flags);



	val = clk_readl(phase->reg);

	val &= ~phase->mask;

	val |= regval << phase->shift;

	clk_writel(val, phase->reg);



	spin_unlock_irqrestore(phase->lock, flags);



	return 0;

}



const struct clk_ops clk_phase_ops = {

	.get_phase = hisi_clk_get_phase,

	.set_phase = hisi_clk_set_phase,

};



struct clk *clk_register_hisi_phase(struct device *dev,

		const struct hisi_phase_clock *clks,

		void __iomem *base, spinlock_t *lock)

{

	struct clk_hisi_phase *phase;

	struct clk_init_data init;



	phase = devm_kzalloc(dev, sizeof(struct clk_hisi_phase), GFP_KERNEL);

	if (!phase)

		return ERR_PTR(-ENOMEM);



	init.name = clks->name;

	init.ops = &clk_phase_ops;

	init.flags = clks->flags | CLK_IS_BASIC;

	init.parent_names = clks->parent_names ? &clks->parent_names : NULL;

	init.num_parents = clks->parent_names ? 1 : 0;



	phase->reg = base + clks->offset;

	phase->shift = clks->shift;

	phase->mask = (BIT(clks->width) - 1) << clks->shift;

	phase->lock = lock;

	phase->phase_degrees = clks->phase_degrees;

	phase->phase_regvals = clks->phase_regvals;

	phase->phase_num = clks->phase_num;

	phase->hw.init = &init;



	return devm_clk_register(dev, &phase->hw);

}

EXPORT_SYMBOL_GPL(clk_register_hisi_phase);

drivers/clk/hisilicon/clk.c

+24 −0
Original line number Diff line number Diff line
@@ -197,6 +197,30 @@ err: 
}

EXPORT_SYMBOL_GPL(hisi_clk_register_mux);



int hisi_clk_register_phase(struct device *dev,

			    const struct hisi_phase_clock *clks,

			    int nums, struct hisi_clock_data *data)

{

	void __iomem *base = data->base;

	struct clk *clk;

	int i;



	for (i = 0; i < nums; i++) {

		clk = clk_register_hisi_phase(dev, &clks[i], base,

					      &hisi_clk_lock);

		if (IS_ERR(clk)) {

			pr_err("%s: failed to register clock %s\n", __func__,

			       clks[i].name);

			return PTR_ERR(clk);

		}



		data->clk_data.clks[clks[i].id] = clk;

	}



	return 0;

}

EXPORT_SYMBOL_GPL(hisi_clk_register_phase);



int hisi_clk_register_divider(const struct hisi_divider_clock *clks,

				      int nums, struct hisi_clock_data *data)

{

drivers/clk/hisilicon/clk.h

+19 −0
Original line number Diff line number Diff line
@@ -68,6 +68,19 @@ struct hisi_mux_clock { 
	const char		*alias;

};



struct hisi_phase_clock {

	unsigned int		id;

	const char		*name;

	const char		*parent_names;

	unsigned long		flags;

	unsigned long		offset;

	u8			shift;

	u8			width;

	u32			*phase_degrees;

	u32			*phase_regvals;

	u8			phase_num;

};



struct hisi_divider_clock {

	unsigned int		id;

	const char		*name;
@@ -120,6 +133,12 @@ int hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *, 
				int, struct hisi_clock_data *);

int hisi_clk_register_mux(const struct hisi_mux_clock *, int,

				struct hisi_clock_data *);

struct clk *clk_register_hisi_phase(struct device *dev,

				const struct hisi_phase_clock *clks,

				void __iomem *base, spinlock_t *lock);

int hisi_clk_register_phase(struct device *dev,

				const struct hisi_phase_clock *clks,

				int nums, struct hisi_clock_data *data);

int hisi_clk_register_divider(const struct hisi_divider_clock *,

				int, struct hisi_clock_data *);

int hisi_clk_register_gate(const struct hisi_gate_clock *,

drivers/clk/hisilicon/crg-hi3798cv200.c

+64 −36
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ 
#define HI3798CV200_FIXED_60M			83

#define HI3798CV200_FIXED_166P5M		84

#define HI3798CV200_SDIO0_MUX			85

#define HI3798CV200_COMBPHY0_MUX		86



#define HI3798CV200_CRG_NR_CLKS			128
@@ -74,9 +75,9 @@ static const char *const mmc_mux_p[] = { 
		"100m", "50m", "25m", "200m", "150m" };

static u32 mmc_mux_table[] = {0, 1, 2, 3, 6};



static const char *const comphy1_mux_p[] = {

static const char *const comphy_mux_p[] = {

		"100m", "25m"};

static u32 comphy1_mux_table[] = {2, 3};

static u32 comphy_mux_table[] = {2, 3};



static const char *const sdio_mux_p[] = {

		"100m", "50m", "150m", "166p5m" };
@@ -85,14 +86,29 @@ static u32 sdio_mux_table[] = {0, 1, 2, 3}; 
static struct hisi_mux_clock hi3798cv200_mux_clks[] = {

	{ HI3798CV200_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),

		CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, },

	{ HI3798CV200_COMBPHY0_MUX, "combphy0_mux",

		comphy_mux_p, ARRAY_SIZE(comphy_mux_p),

		CLK_SET_RATE_PARENT, 0x188, 2, 2, 0, comphy_mux_table, },

	{ HI3798CV200_COMBPHY1_MUX, "combphy1_mux",

		comphy1_mux_p, ARRAY_SIZE(comphy1_mux_p),

		CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy1_mux_table, },

		comphy_mux_p, ARRAY_SIZE(comphy_mux_p),

		CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy_mux_table, },

	{ HI3798CV200_SDIO0_MUX, "sdio0_mux", sdio_mux_p,

		ARRAY_SIZE(sdio_mux_p), CLK_SET_RATE_PARENT,

		0x9c, 8, 2, 0, sdio_mux_table, },

};



static u32 mmc_phase_regvals[] = {0, 1, 2, 3, 4, 5, 6, 7};

static u32 mmc_phase_degrees[] = {0, 45, 90, 135, 180, 225, 270, 315};



static struct hisi_phase_clock hi3798cv200_phase_clks[] = {

	{ HISTB_MMC_SAMPLE_CLK, "mmc_sample", "clk_mmc_ciu",

		CLK_SET_RATE_PARENT, 0xa0, 12, 3, mmc_phase_degrees,

		mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) },

	{ HISTB_MMC_DRV_CLK, "mmc_drive", "clk_mmc_ciu",

		CLK_SET_RATE_PARENT, 0xa0, 16, 3, mmc_phase_degrees,

		mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) },

};



static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {

	/* UART */

	{ HISTB_UART2_CLK, "clk_uart2", "75m",
@@ -147,6 +163,9 @@ static const struct hisi_gate_clock hi3798cv200_gate_clks[] = { 
		CLK_SET_RATE_PARENT, 0xcc, 4, 0, },

	{ HISTB_ETH1_MACIF_CLK, "clk_macif1", "clk_bus_m1",

		CLK_SET_RATE_PARENT, 0xcc, 25, 0, },

	/* COMBPHY0 */

	{ HISTB_COMBPHY0_CLK, "clk_combphy0", "combphy0_mux",

		CLK_SET_RATE_PARENT, 0x188, 0, 0, },

	/* COMBPHY1 */

	{ HISTB_COMBPHY1_CLK, "clk_combphy1", "combphy1_mux",

		CLK_SET_RATE_PARENT, 0x188, 8, 0, },
@@ -161,6 +180,8 @@ static const struct hisi_gate_clock hi3798cv200_gate_clks[] = { 
		CLK_SET_RATE_PARENT, 0xb8, 1, 0 },

	{ HISTB_USB2_UTMI_CLK, "clk_u2_utmi", "60m",

		CLK_SET_RATE_PARENT, 0xb8, 5, 0 },

	{ HISTB_USB2_OTG_UTMI_CLK, "clk_u2_otg_utmi", "60m",

		CLK_SET_RATE_PARENT, 0xb8, 3, 0 },

	{ HISTB_USB2_PHY1_REF_CLK, "clk_u2_phy1_ref", "24m",

		CLK_SET_RATE_PARENT, 0xbc, 0, 0 },

	{ HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m",
@@ -177,6 +198,14 @@ static struct hisi_clock_data *hi3798cv200_clk_register( 
	if (!clk_data)

		return ERR_PTR(-ENOMEM);



	/* hisi_phase_clock is resource managed */

	ret = hisi_clk_register_phase(&pdev->dev,

				hi3798cv200_phase_clks,

				ARRAY_SIZE(hi3798cv200_phase_clks),

				clk_data);

	if (ret)

		return ERR_PTR(ret);



	ret = hisi_clk_register_fixed_rate(hi3798cv200_fixed_rate_clks,

				     ARRAY_SIZE(hi3798cv200_fixed_rate_clks),

				     clk_data);
@@ -202,18 +231,17 @@ static struct hisi_clock_data *hi3798cv200_clk_register( 


	return clk_data;



unregister_fixed_rate:

	hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks,

				ARRAY_SIZE(hi3798cv200_fixed_rate_clks),

unregister_gate:

	hisi_clk_unregister_gate(hi3798cv200_gate_clks,

				ARRAY_SIZE(hi3798cv200_gate_clks),

				clk_data);



unregister_mux:

	hisi_clk_unregister_mux(hi3798cv200_mux_clks,

				ARRAY_SIZE(hi3798cv200_mux_clks),

				clk_data);

unregister_gate:

	hisi_clk_unregister_gate(hi3798cv200_gate_clks,

				ARRAY_SIZE(hi3798cv200_gate_clks),

unregister_fixed_rate:

	hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks,

				ARRAY_SIZE(hi3798cv200_fixed_rate_clks),

				clk_data);

	return ERR_PTR(ret);

}
@@ -245,7 +273,7 @@ static const struct hisi_crg_funcs hi3798cv200_crg_funcs = { 
#define HI3798CV200_SYSCTRL_NR_CLKS 16



static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = {

	{ HISTB_IR_CLK, "clk_ir", "100m",

	{ HISTB_IR_CLK, "clk_ir", "24m",

		CLK_SET_RATE_PARENT, 0x48, 4, 0, },

	{ HISTB_TIMER01_CLK, "clk_timer01", "24m",

		CLK_SET_RATE_PARENT, 0x48, 6, 0, },

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