Commit e2464688 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS updates from Ralf Baechle:
 "This is the main pull request for MIPS for 4.5 plus some 4.4 fixes.

  The executive summary:

   - ATH79 platform improvments, use DT bindings for the ATH79 USB PHY.
   - Avoid useless rebuilds for zboot.
   - jz4780: Add NEMC, BCH and NAND device tree nodes
   - Initial support for the MicroChip's DT platform.  As all the device
     drivers are missing this is still of limited use.
   - Some Loongson3 cleanups.
   - The unavoidable whitespace polishing.
   - Reduce clock skew when synchronizing the CPU cycle counters on CPU
     startup.
   - Add MIPS R6 fixes.
   - Lots of cleanups across arch/mips as fallout from KVM.
   - Lots of minor fixes and changes for IEEE 754-2008 support to the
     FPU emulator / fp-assist software.
   - Minor Ralink, BCM47xx and bcm963xx platform support improvments.
   - Support SMP on BCM63168"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (84 commits)
  MIPS: zboot: Add support for serial debug using the PROM
  MIPS: zboot: Avoid useless rebuilds
  MIPS: BMIPS: Enable ARCH_WANT_OPTIONAL_GPIOLIB
  MIPS: bcm63xx: nvram: Remove unused bcm63xx_nvram_get_psi_size() function
  MIPS: bcm963xx: Update bcm_tag field image_sequence
  MIPS: bcm963xx: Move extended flash address to bcm_tag header file
  MIPS: bcm963xx: Move Broadcom BCM963xx image tag data structure
  MIPS: bcm63xx: nvram: Use nvram structure definition from header file
  MIPS: bcm963xx: Add Broadcom BCM963xx board nvram data structure
  MAINTAINERS: Add KVM for MIPS entry
  MIPS: KVM: Add missing newline to kvm_err()
  MIPS: Move KVM specific opcodes into asm/inst.h
  MIPS: KVM: Use cacheops.h definitions
  MIPS: Break down cacheops.h definitions
  MIPS: Use EXCCODE_ constants with set_except_vector()
  MIPS: Update trap codes
  MIPS: Move Cause.ExcCode trap codes to mipsregs.h
  MIPS: KVM: Make kvm_mips_{init,exit}() static
  MIPS: KVM: Refactor added offsetof()s
  MIPS: KVM: Convert EXPORT_SYMBOL to _GPL
  ...
parents e1c10879 07d17f09

Documentation/devicetree/bindings/interrupt-controller/microchip,pic32-evic.txt

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Microchip PIC32 Interrupt Controller

====================================



The Microchip PIC32 contains an Enhanced Vectored Interrupt Controller (EVIC).

It handles all internal and external interrupts. This controller exists outside

of the CPU and is the arbitrator of all interrupts (including interrupts from

the CPU itself) before they are presented to the CPU.



External interrupts have a software configurable edge polarity. Non external

interrupts have a type and polarity that is determined by the source of the

interrupt.



Required properties

-------------------



- compatible: Should be "microchip,pic32mzda-evic"

- reg: Specifies physical base address and size of register range.

- interrupt-controller: Identifies the node as an interrupt controller.

- #interrupt cells: Specifies the number of cells used to encode an interrupt

  source connected to this controller. The value shall be 2 and interrupt

  descriptor shall have the following format:



	<hw_irq irq_type>



  hw_irq - represents the hardware interrupt number as in the data sheet.

  irq_type - is used to describe the type and polarity of an interrupt. For

  internal interrupts use IRQ_TYPE_EDGE_RISING for non persistent interrupts and

  IRQ_TYPE_LEVEL_HIGH for persistent interrupts. For external interrupts use

  IRQ_TYPE_EDGE_RISING or IRQ_TYPE_EDGE_FALLING to select the desired polarity.



Optional properties

-------------------

- microchip,external-irqs: u32 array of external interrupts with software

  polarity configuration. This array corresponds to the bits in the INTCON

  SFR.



Example

-------



evic: interrupt-controller@1f810000 {

	compatible = "microchip,pic32mzda-evic";

	interrupt-controller;

	#interrupt-cells = <2>;

	reg = <0x1f810000 0x1000>;

	microchip,external-irqs = <3 8 13 18 23>;

};



Each device/peripheral must request its interrupt line with the associated type

and polarity.



Internal interrupt DTS snippet

------------------------------



device@1f800000 {

	...

	interrupts = <113 IRQ_TYPE_LEVEL_HIGH>;

	...

};



External interrupt DTS snippet

------------------------------



device@1f800000 {

	...

	interrupts = <3 IRQ_TYPE_EDGE_RISING>;

	...

};

Documentation/devicetree/bindings/mips/pic32/microchip,pic32mzda.txt

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* Microchip PIC32MZDA Platforms



PIC32MZDA Starter Kit

Required root node properties:

    - compatible = "microchip,pic32mzda-sk", "microchip,pic32mzda"



CPU nodes:

----------

A "cpus" node is required.  Required properties:

 - #address-cells: Must be 1.

 - #size-cells: Must be 0.

A CPU sub-node is also required.  Required properties:

 - device_type: Must be "cpu".

 - compatible: Must be "mti,mips14KEc".

Example:

	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "mti,mips14KEc";

		};

	};



Boot protocol

--------------

In accordance with Unified Hosting Interface Reference Manual (MD01069), the

bootloader must pass the following arguments to the kernel:

 - $a0: -2.

 - $a1: KSEG0 address of the flattened device-tree blob.

Documentation/devicetree/bindings/net/mediatek,mt7620-gsw.txt

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Mediatek Gigabit Switch

=======================



The mediatek gigabit switch can be found on Mediatek SoCs (mt7620, mt7621).



Required properties:

- compatible: Should be "mediatek,mt7620-gsw" or "mediatek,mt7621-gsw"

- reg: Address and length of the register set for the device

- interrupt-parent: Should be the phandle for the interrupt controller

  that services interrupts for this device

- interrupts: Should contain the gigabit switches interrupt

- resets: Should contain the gigabit switches resets

- reset-names: Should contain the reset names "gsw"



Example:



gsw@10110000 {

	compatible = "ralink,mt7620-gsw";

	reg = <0x10110000 8000>;



	resets = <&rstctrl 23>;

	reset-names = "gsw";



	interrupt-parent = <&intc>;

	interrupts = <17>;

};

Documentation/devicetree/bindings/net/ralink,rt2880-net.txt

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Ralink Frame Engine Ethernet controller

=======================================



The Ralink frame engine ethernet controller can be found on Ralink and

Mediatek SoCs (RT288x, RT3x5x, RT366x, RT388x, rt5350, mt7620, mt7621, mt76x8).



Depending on the SoC, there is a number of ports connected to the CPU port

directly and/or via a (gigabit-)switch.



* Ethernet controller node



Required properties:

- compatible: Should be one of "ralink,rt2880-eth", "ralink,rt3050-eth",

  "ralink,rt3050-eth", "ralink,rt3883-eth", "ralink,rt5350-eth",

  "mediatek,mt7620-eth", "mediatek,mt7621-eth"

- reg: Address and length of the register set for the device

- interrupt-parent: Should be the phandle for the interrupt controller

  that services interrupts for this device

- interrupts: Should contain the frame engines interrupt

- resets: Should contain the frame engines resets

- reset-names: Should contain the reset names "fe". If a switch is present

  "esw" is also required.





* Ethernet port node



Required properties:

- compatible: Should be "ralink,eth-port"

- reg: The number of the physical port

- phy-handle: reference to the node describing the phy



Example:



mdio-bus {

	...

	phy0: ethernet-phy@0 {

		phy-mode = "mii";

		reg = <0>;

	};

};



ethernet@400000 {

	compatible = "ralink,rt2880-eth";

	reg = <0x00400000 10000>;



	#address-cells = <1>;

	#size-cells = <0>;



	resets = <&rstctrl 18>;

	reset-names = "fe";



	interrupt-parent = <&cpuintc>;

	interrupts = <5>;



	port@0 {

		compatible = "ralink,eth-port";

		reg = <0>;

		phy-handle = <&phy0>;

	};



};

Documentation/devicetree/bindings/net/ralink,rt3050-esw.txt

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Ralink Fast Ethernet Embedded Switch

====================================



The ralink fast ethernet embedded switch can be found on Ralink and Mediatek

SoCs (RT3x5x, RT5350, MT76x8).



Required properties:

- compatible: Should be "ralink,rt3050-esw"

- reg: Address and length of the register set for the device

- interrupt-parent: Should be the phandle for the interrupt controller

  that services interrupts for this device

- interrupts: Should contain the embedded switches interrupt

- resets: Should contain the embedded switches resets

- reset-names: Should contain the reset names "esw"



Optional properties:

- ralink,portmap: can be used to choose if the default switch setup is

  llllw or wllll

- ralink,led_polarity: override the active high/low settings of the leds



Example:



esw@10110000 {

	compatible = "ralink,rt3050-esw";

	reg = <0x10110000 8000>;



	resets = <&rstctrl 23>;

	reset-names = "esw";



	interrupt-parent = <&intc>;

	interrupts = <17>;

};

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