clk: bcm63xx-gate: switch to dt-bindings definitions (e244d205) · Commits · 戴 / test

drivers/clk/bcm/clk-bcm63xx-gate.c

+439 −141

Original line number	Diff line number	Diff line
		@@ -6,6 +6,14 @@
		#include <linux/of_device.h>
		#include <linux/platform_device.h>

		#include <dt-bindings/clock/bcm3368-clock.h>
		#include <dt-bindings/clock/bcm6318-clock.h>
		#include <dt-bindings/clock/bcm6328-clock.h>
		#include <dt-bindings/clock/bcm6358-clock.h>
		#include <dt-bindings/clock/bcm6362-clock.h>
		#include <dt-bindings/clock/bcm6368-clock.h>
		#include <dt-bindings/clock/bcm63268-clock.h>

		struct clk_bcm63xx_table_entry {
		const char * const name;
		u8 bit;
		@@ -20,168 +28,458 @@ struct clk_bcm63xx_hw {
		};

		static const struct clk_bcm63xx_table_entry bcm3368_clocks[] = {
		{ .name = "mac", .bit = 3, },
		{ .name = "tc", .bit = 5, },
		{ .name = "us_top", .bit = 6, },
		{ .name = "ds_top", .bit = 7, },
		{ .name = "acm", .bit = 8, },
		{ .name = "spi", .bit = 9, },
		{ .name = "usbs", .bit = 10, },
		{ .name = "bmu", .bit = 11, },
		{ .name = "pcm", .bit = 12, },
		{ .name = "ntp", .bit = 13, },
		{ .name = "acp_b", .bit = 14, },
		{ .name = "acp_a", .bit = 15, },
		{ .name = "emusb", .bit = 17, },
		{ .name = "enet0", .bit = 18, },
		{ .name = "enet1", .bit = 19, },
		{ .name = "usbsu", .bit = 20, },
		{ .name = "ephy", .bit = 21, },
		{ },
		{
		.name = "mac",
		.bit = BCM3368_CLK_MAC,
		}, {
		.name = "tc",
		.bit = BCM3368_CLK_TC,
		}, {
		.name = "us_top",
		.bit = BCM3368_CLK_US_TOP,
		}, {
		.name = "ds_top",
		.bit = BCM3368_CLK_DS_TOP,
		}, {
		.name = "acm",
		.bit = BCM3368_CLK_ACM,
		}, {
		.name = "spi",
		.bit = BCM3368_CLK_SPI,
		}, {
		.name = "usbs",
		.bit = BCM3368_CLK_USBS,
		}, {
		.name = "bmu",
		.bit = BCM3368_CLK_BMU,
		}, {
		.name = "pcm",
		.bit = BCM3368_CLK_PCM,
		}, {
		.name = "ntp",
		.bit = BCM3368_CLK_NTP,
		}, {
		.name = "acp_b",
		.bit = BCM3368_CLK_ACP_B,
		}, {
		.name = "acp_a",
		.bit = BCM3368_CLK_ACP_A,
		}, {
		.name = "emusb",
		.bit = BCM3368_CLK_EMUSB,
		}, {
		.name = "enet0",
		.bit = BCM3368_CLK_ENET0,
		}, {
		.name = "enet1",
		.bit = BCM3368_CLK_ENET1,
		}, {
		.name = "usbsu",
		.bit = BCM3368_CLK_USBSU,
		}, {
		.name = "ephy",
		.bit = BCM3368_CLK_EPHY,
		}, {
		/* sentinel */
		},
		};

		static const struct clk_bcm63xx_table_entry bcm6318_clocks[] = {
		{ .name = "adsl_asb", .bit = 0, },
		{ .name = "usb_asb", .bit = 1, },
		{ .name = "mips_asb", .bit = 2, },
		{ .name = "pcie_asb", .bit = 3, },
		{ .name = "phymips_asb", .bit = 4, },
		{ .name = "robosw_asb", .bit = 5, },
		{ .name = "sar_asb", .bit = 6, },
		{ .name = "sdr_asb", .bit = 7, },
		{ .name = "swreg_asb", .bit = 8, },
		{ .name = "periph_asb", .bit = 9, },
		{ .name = "cpubus160", .bit = 10, },
		{ .name = "adsl", .bit = 11, },
		{ .name = "sar125", .bit = 12, },
		{ .name = "mips", .bit = 13, .flags = CLK_IS_CRITICAL, },
		{ .name = "pcie", .bit = 14, },
		{ .name = "robosw250", .bit = 16, },
		{ .name = "robosw025", .bit = 17, },
		{ .name = "sdr", .bit = 19, .flags = CLK_IS_CRITICAL, },
		{ .name = "usbd", .bit = 20, },
		{ .name = "hsspi", .bit = 25, },
		{ .name = "pcie25", .bit = 27, },
		{ .name = "phymips", .bit = 28, },
		{ .name = "afe", .bit = 29, },
		{ .name = "qproc", .bit = 30, },
		{ },
		{
		.name = "adsl_asb",
		.bit = BCM6318_CLK_ADSL_ASB,
		}, {
		.name = "usb_asb",
		.bit = BCM6318_CLK_USB_ASB,
		}, {
		.name = "mips_asb",
		.bit = BCM6318_CLK_MIPS_ASB,
		}, {
		.name = "pcie_asb",
		.bit = BCM6318_CLK_PCIE_ASB,
		}, {
		.name = "phymips_asb",
		.bit = BCM6318_CLK_PHYMIPS_ASB,
		}, {
		.name = "robosw_asb",
		.bit = BCM6318_CLK_ROBOSW_ASB,
		}, {
		.name = "sar_asb",
		.bit = BCM6318_CLK_SAR_ASB,
		}, {
		.name = "sdr_asb",
		.bit = BCM6318_CLK_SDR_ASB,
		}, {
		.name = "swreg_asb",
		.bit = BCM6318_CLK_SWREG_ASB,
		}, {
		.name = "periph_asb",
		.bit = BCM6318_CLK_PERIPH_ASB,
		}, {
		.name = "cpubus160",
		.bit = BCM6318_CLK_CPUBUS160,
		}, {
		.name = "adsl",
		.bit = BCM6318_CLK_ADSL,
		}, {
		.name = "sar125",
		.bit = BCM6318_CLK_SAR125,
		}, {
		.name = "mips",
		.bit = BCM6318_CLK_MIPS,
		.flags = CLK_IS_CRITICAL,
		}, {
		.name = "pcie",
		.bit = BCM6318_CLK_PCIE,
		}, {
		.name = "robosw250",
		.bit = BCM6318_CLK_ROBOSW250,
		}, {
		.name = "robosw025",
		.bit = BCM6318_CLK_ROBOSW025,
		}, {
		.name = "sdr",
		.bit = BCM6318_CLK_SDR,
		.flags = CLK_IS_CRITICAL,
		}, {
		.name = "usbd",
		.bit = BCM6318_CLK_USBD,
		}, {
		.name = "hsspi",
		.bit = BCM6318_CLK_HSSPI,
		}, {
		.name = "pcie25",
		.bit = BCM6318_CLK_PCIE25,
		}, {
		.name = "phymips",
		.bit = BCM6318_CLK_PHYMIPS,
		}, {
		.name = "afe",
		.bit = BCM6318_CLK_AFE,
		}, {
		.name = "qproc",
		.bit = BCM6318_CLK_QPROC,
		}, {
		/* sentinel */
		},
		};

		static const struct clk_bcm63xx_table_entry bcm6318_ubus_clocks[] = {
		{ .name = "adsl-ubus", .bit = 0, },
		{ .name = "arb-ubus", .bit = 1, .flags = CLK_IS_CRITICAL, },
		{ .name = "mips-ubus", .bit = 2, .flags = CLK_IS_CRITICAL, },
		{ .name = "pcie-ubus", .bit = 3, },
		{ .name = "periph-ubus", .bit = 4, .flags = CLK_IS_CRITICAL, },
		{ .name = "phymips-ubus", .bit = 5, },
		{ .name = "robosw-ubus", .bit = 6, },
		{ .name = "sar-ubus", .bit = 7, },
		{ .name = "sdr-ubus", .bit = 8, },
		{ .name = "usb-ubus", .bit = 9, },
		{ },
		{
		.name = "adsl-ubus",
		.bit = BCM6318_UCLK_ADSL,
		}, {
		.name = "arb-ubus",
		.bit = BCM6318_UCLK_ARB,
		.flags = CLK_IS_CRITICAL,
		}, {
		.name = "mips-ubus",
		.bit = BCM6318_UCLK_MIPS,
		.flags = CLK_IS_CRITICAL,
		}, {
		.name = "pcie-ubus",
		.bit = BCM6318_UCLK_PCIE,
		}, {
		.name = "periph-ubus",
		.bit = BCM6318_UCLK_PERIPH,
		.flags = CLK_IS_CRITICAL,
		}, {
		.name = "phymips-ubus",
		.bit = BCM6318_UCLK_PHYMIPS,
		}, {
		.name = "robosw-ubus",
		.bit = BCM6318_UCLK_ROBOSW,
		}, {
		.name = "sar-ubus",
		.bit = BCM6318_UCLK_SAR,
		}, {
		.name = "sdr-ubus",
		.bit = BCM6318_UCLK_SDR,
		}, {
		.name = "usb-ubus",
		.bit = BCM6318_UCLK_USB,
		}, {
		/* sentinel */
		},
		};

		static const struct clk_bcm63xx_table_entry bcm6328_clocks[] = {
		{ .name = "phy_mips", .bit = 0, },
		{ .name = "adsl_qproc", .bit = 1, },
		{ .name = "adsl_afe", .bit = 2, },
		{ .name = "adsl", .bit = 3, },
		{ .name = "mips", .bit = 4, .flags = CLK_IS_CRITICAL, },
		{ .name = "sar", .bit = 5, },
		{ .name = "pcm", .bit = 6, },
		{ .name = "usbd", .bit = 7, },
		{ .name = "usbh", .bit = 8, },
		{ .name = "hsspi", .bit = 9, },
		{ .name = "pcie", .bit = 10, },
		{ .name = "robosw", .bit = 11, },
		{ },
		{
		.name = "phy_mips",
		.bit = BCM6328_CLK_PHYMIPS,
		}, {
		.name = "adsl_qproc",
		.bit = BCM6328_CLK_ADSL_QPROC,
		}, {
		.name = "adsl_afe",
		.bit = BCM6328_CLK_ADSL_AFE,
		}, {
		.name = "adsl",
		.bit = BCM6328_CLK_ADSL,
		}, {
		.name = "mips",
		.bit = BCM6328_CLK_MIPS,
		.flags = CLK_IS_CRITICAL,
		}, {
		.name = "sar",
		.bit = BCM6328_CLK_SAR,
		}, {
		.name = "pcm",
		.bit = BCM6328_CLK_PCM,
		}, {
		.name = "usbd",
		.bit = BCM6328_CLK_USBD,
		}, {
		.name = "usbh",
		.bit = BCM6328_CLK_USBH,
		}, {
		.name = "hsspi",
		.bit = BCM6328_CLK_HSSPI,
		}, {
		.name = "pcie",
		.bit = BCM6328_CLK_PCIE,
		}, {
		.name = "robosw",
		.bit = BCM6328_CLK_ROBOSW,
		}, {
		/* sentinel */
		},
		};

		static const struct clk_bcm63xx_table_entry bcm6358_clocks[] = {
		{ .name = "enet", .bit = 4, },
		{ .name = "adslphy", .bit = 5, },
		{ .name = "pcm", .bit = 8, },
		{ .name = "spi", .bit = 9, },
		{ .name = "usbs", .bit = 10, },
		{ .name = "sar", .bit = 11, },
		{ .name = "emusb", .bit = 17, },
		{ .name = "enet0", .bit = 18, },
		{ .name = "enet1", .bit = 19, },
		{ .name = "usbsu", .bit = 20, },
		{ .name = "ephy", .bit = 21, },
		{ },
		{
		.name = "enet",
		.bit = BCM6358_CLK_ENET,
		}, {
		.name = "adslphy",
		.bit = BCM6358_CLK_ADSLPHY,
		}, {
		.name = "pcm",
		.bit = BCM6358_CLK_PCM,
		}, {
		.name = "spi",
		.bit = BCM6358_CLK_SPI,
		}, {
		.name = "usbs",
		.bit = BCM6358_CLK_USBS,
		}, {
		.name = "sar",
		.bit = BCM6358_CLK_SAR,
		}, {
		.name = "emusb",
		.bit = BCM6358_CLK_EMUSB,
		}, {
		.name = "enet0",
		.bit = BCM6358_CLK_ENET0,
		}, {
		.name = "enet1",
		.bit = BCM6358_CLK_ENET1,
		}, {
		.name = "usbsu",
		.bit = BCM6358_CLK_USBSU,
		}, {
		.name = "ephy",
		.bit = BCM6358_CLK_EPHY,
		}, {
		/* sentinel */
		},
		};

		static const struct clk_bcm63xx_table_entry bcm6362_clocks[] = {
		{ .name = "adsl_qproc", .bit = 1, },
		{ .name = "adsl_afe", .bit = 2, },
		{ .name = "adsl", .bit = 3, },
		{ .name = "mips", .bit = 4, .flags = CLK_IS_CRITICAL, },
		{ .name = "wlan_ocp", .bit = 5, },
		{ .name = "swpkt_usb", .bit = 7, },
		{ .name = "swpkt_sar", .bit = 8, },
		{ .name = "sar", .bit = 9, },
		{ .name = "robosw", .bit = 10, },
		{ .name = "pcm", .bit = 11, },
		{ .name = "usbd", .bit = 12, },
		{ .name = "usbh", .bit = 13, },
		{ .name = "ipsec", .bit = 14, },
		{ .name = "spi", .bit = 15, },
		{ .name = "hsspi", .bit = 16, },
		{ .name = "pcie", .bit = 17, },
		{ .name = "fap", .bit = 18, },
		{ .name = "phymips", .bit = 19, },
		{ .name = "nand", .bit = 20, },
		{ },
		{
		.name = "adsl_qproc",
		.bit = BCM6362_CLK_ADSL_QPROC,
		}, {
		.name = "adsl_afe",
		.bit = BCM6362_CLK_ADSL_AFE,
		}, {
		.name = "adsl",
		.bit = BCM6362_CLK_ADSL,
		}, {
		.name = "mips",
		.bit = BCM6362_CLK_MIPS,
		.flags = CLK_IS_CRITICAL,
		}, {
		.name = "wlan_ocp",
		.bit = BCM6362_CLK_WLAN_OCP,
		}, {
		.name = "swpkt_usb",
		.bit = BCM6362_CLK_SWPKT_USB,
		}, {
		.name = "swpkt_sar",
		.bit = BCM6362_CLK_SWPKT_SAR,
		}, {
		.name = "sar",
		.bit = BCM6362_CLK_SAR,
		}, {
		.name = "robosw",
		.bit = BCM6362_CLK_ROBOSW,
		}, {
		.name = "pcm",
		.bit = BCM6362_CLK_PCM,
		}, {
		.name = "usbd",
		.bit = BCM6362_CLK_USBD,
		}, {
		.name = "usbh",
		.bit = BCM6362_CLK_USBH,
		}, {
		.name = "ipsec",
		.bit = BCM6362_CLK_IPSEC,
		}, {
		.name = "spi",
		.bit = BCM6362_CLK_SPI,
		}, {
		.name = "hsspi",
		.bit = BCM6362_CLK_HSSPI,
		}, {
		.name = "pcie",
		.bit = BCM6362_CLK_PCIE,
		}, {
		.name = "fap",
		.bit = BCM6362_CLK_FAP,
		}, {
		.name = "phymips",
		.bit = BCM6362_CLK_PHYMIPS,
		}, {
		.name = "nand",
		.bit = BCM6362_CLK_NAND,
		}, {
		/* sentinel */
		},
		};

		static const struct clk_bcm63xx_table_entry bcm6368_clocks[] = {
		{ .name = "vdsl_qproc", .bit = 2, },
		{ .name = "vdsl_afe", .bit = 3, },
		{ .name = "vdsl_bonding", .bit = 4, },
		{ .name = "vdsl", .bit = 5, },
		{ .name = "phymips", .bit = 6, },
		{ .name = "swpkt_usb", .bit = 7, },
		{ .name = "swpkt_sar", .bit = 8, },
		{ .name = "spi", .bit = 9, },
		{ .name = "usbd", .bit = 10, },
		{ .name = "sar", .bit = 11, },
		{ .name = "robosw", .bit = 12, },
		{ .name = "utopia", .bit = 13, },
		{ .name = "pcm", .bit = 14, },
		{ .name = "usbh", .bit = 15, },
		{ .name = "disable_gless", .bit = 16, },
		{ .name = "nand", .bit = 17, },
		{ .name = "ipsec", .bit = 18, },
		{ },
		{
		.name = "vdsl_qproc",
		.bit = BCM6368_CLK_VDSL_QPROC,
		}, {
		.name = "vdsl_afe",
		.bit = BCM6368_CLK_VDSL_AFE,
		}, {
		.name = "vdsl_bonding",
		.bit = BCM6368_CLK_VDSL_BONDING,
		}, {
		.name = "vdsl",
		.bit = BCM6368_CLK_VDSL,
		}, {
		.name = "phymips",
		.bit = BCM6368_CLK_PHYMIPS,
		}, {
		.name = "swpkt_usb",
		.bit = BCM6368_CLK_SWPKT_USB,
		}, {
		.name = "swpkt_sar",
		.bit = BCM6368_CLK_SWPKT_SAR,
		}, {
		.name = "spi",
		.bit = BCM6368_CLK_SPI,
		}, {
		.name = "usbd",
		.bit = BCM6368_CLK_USBD,
		}, {
		.name = "sar",
		.bit = BCM6368_CLK_SAR,
		}, {
		.name = "robosw",
		.bit = BCM6368_CLK_ROBOSW,
		}, {
		.name = "utopia",
		.bit = BCM6368_CLK_UTOPIA,
		}, {
		.name = "pcm",
		.bit = BCM6368_CLK_PCM,
		}, {
		.name = "usbh",
		.bit = BCM6368_CLK_USBH,
		}, {
		.name = "disable_gless",
		.bit = BCM6368_CLK_DIS_GLESS,
		}, {
		.name = "nand",
		.bit = BCM6368_CLK_NAND,
		}, {
		.name = "ipsec",
		.bit = BCM6368_CLK_IPSEC,
		}, {
		/* sentinel */
		},
		};

		static const struct clk_bcm63xx_table_entry bcm63268_clocks[] = {
		{ .name = "disable_gless", .bit = 0, },
		{ .name = "vdsl_qproc", .bit = 1, },
		{ .name = "vdsl_afe", .bit = 2, },
		{ .name = "vdsl", .bit = 3, },
		{ .name = "mips", .bit = 4, .flags = CLK_IS_CRITICAL, },
		{ .name = "wlan_ocp", .bit = 5, },
		{ .name = "dect", .bit = 6, },
		{ .name = "fap0", .bit = 7, },
		{ .name = "fap1", .bit = 8, },
		{ .name = "sar", .bit = 9, },
		{ .name = "robosw", .bit = 10, },
		{ .name = "pcm", .bit = 11, },
		{ .name = "usbd", .bit = 12, },
		{ .name = "usbh", .bit = 13, },
		{ .name = "ipsec", .bit = 14, },
		{ .name = "spi", .bit = 15, },
		{ .name = "hsspi", .bit = 16, },
		{ .name = "pcie", .bit = 17, },
		{ .name = "phymips", .bit = 18, },
		{ .name = "gmac", .bit = 19, },
		{ .name = "nand", .bit = 20, },
		{ .name = "tbus", .bit = 27, },
		{ .name = "robosw250", .bit = 31, },
		{ },
		{
		.name = "disable_gless",
		.bit = BCM63268_CLK_DIS_GLESS,
		}, {
		.name = "vdsl_qproc",
		.bit = BCM63268_CLK_VDSL_QPROC,
		}, {
		.name = "vdsl_afe",
		.bit = BCM63268_CLK_VDSL_AFE,
		}, {
		.name = "vdsl",
		.bit = BCM63268_CLK_VDSL,
		}, {
		.name = "mips",
		.bit = BCM63268_CLK_MIPS,
		.flags = CLK_IS_CRITICAL,
		}, {
		.name = "wlan_ocp",
		.bit = BCM63268_CLK_WLAN_OCP,
		}, {
		.name = "dect",
		.bit = BCM63268_CLK_DECT,
		}, {
		.name = "fap0",
		.bit = BCM63268_CLK_FAP0,
		}, {
		.name = "fap1",
		.bit = BCM63268_CLK_FAP1,
		}, {
		.name = "sar",
		.bit = BCM63268_CLK_SAR,
		}, {
		.name = "robosw",
		.bit = BCM63268_CLK_ROBOSW,
		}, {
		.name = "pcm",
		.bit = BCM63268_CLK_PCM,
		}, {
		.name = "usbd",
		.bit = BCM63268_CLK_USBD,
		}, {
		.name = "usbh",
		.bit = BCM63268_CLK_USBH,
		}, {
		.name = "ipsec",
		.bit = BCM63268_CLK_IPSEC,
		}, {
		.name = "spi",
		.bit = BCM63268_CLK_SPI,
		}, {
		.name = "hsspi",
		.bit = BCM63268_CLK_HSSPI,
		}, {
		.name = "pcie",
		.bit = BCM63268_CLK_PCIE,
		}, {
		.name = "phymips",
		.bit = BCM63268_CLK_PHYMIPS,
		}, {
		.name = "gmac",
		.bit = BCM63268_CLK_GMAC,
		}, {
		.name = "nand",
		.bit = BCM63268_CLK_NAND,
		}, {
		.name = "tbus",
		.bit = BCM63268_CLK_TBUS,
		}, {
		.name = "robosw250",
		.bit = BCM63268_CLK_ROBOSW250,
		}, {
		/* sentinel */
		},
		};

		static int clk_bcm63xx_probe(struct platform_device *pdev)

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