Commit e21be0d1 authored by Marian Mihailescu's avatar Marian Mihailescu Committed by Sylwester Nawrocki
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clk: samsung: exynos5420: Preserve CPU clocks configuration during suspend/resume 



Save and restore top PLL related configuration registers for big (APLL)
and LITTLE (KPLL) cores during suspend/resume cycle. So far, CPU clocks
were reset to default values after suspend/resume cycle and performance
after system resume was affected when performance governor has been selected.

Fixes: 77342432 ("clk: samsung: exynos5420: add more registers to restore list")
Signed-off-by: default avatarMarian Mihailescu <mihailescu2m@gmail.com>
Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
parent b92981de

drivers/clk/samsung/clk-exynos5420.c

+2 −0
Original line number Diff line number Diff line
@@ -165,6 +165,8 @@ static const unsigned long exynos5x_clk_regs[] __initconst = { 
	GATE_BUS_CPU,

	GATE_SCLK_CPU,

	CLKOUT_CMU_CPU,

	APLL_CON0,

	KPLL_CON0,

	CPLL_CON0,

	DPLL_CON0,

	EPLL_CON0,

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