Commit e1ebb2b4 authored Sep 17, 2020 by Krish Sadhukhan Committed by Borislav Petkov Sep 19, 2020

KVM: SVM: Don't flush cache if hardware enforces cache coherency across encryption domains



In some hardware implementations, coherency between the encrypted and
unencrypted mappings of the same physical page in a VM is enforced. In
such a system, it is not required for software to flush the VM's page
from all CPU caches in the system prior to changing the value of the
C-bit for the page.

So check that bit before flushing the cache.

Signed-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Link: https://lkml.kernel.org/r/20200917212038.5090-4-krish.sadhukhan@oracle.com

parent 75d1cc0e

arch/x86/kvm/svm/sev.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -384,7 +384,8 @@ static void sev_clflush_pages(struct page *pages[], unsigned long npages)
		uint8_t *page_virtual;
		unsigned long i;

		if (npages == 0 \|\| pages == NULL)
		if (this_cpu_has(X86_FEATURE_SME_COHERENT) \|\| npages == 0 \|\|
		pages == NULL)
		return;

		for (i = 0; i < npages; i++) {

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