Commit e1e85e76 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'bcm63138-v4' of http://github.com/brcm/linux into next/soc 

Merge "ARM: BCM: Broadcom BCM63138 support" from Florian Fainelli:

This patchset adds very minimal support for the BCM63138 SoC which is
a xDSL SoC using a dual Cortex A9 CPU complex.

* tag 'bcm63138-v4' of http://github.com/brcm/linux

:
  MAINTAINERS: add entry for the Broadcom BCM63xx ARM SoCs
  ARM: BCM63XX: add BCM963138DVT Reference platform DTS
  ARM: BCM63XX: add BCM63138 minimal Device Tree
  ARM: BCM63XX: add low-level UART debug support
  ARM: BCM63XX: add basic support for the Broadcom BCM63138 DSL SoC

Conflicts:
	arch/arm/Kconfig.debug

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 57e33ff1 e076e962

Documentation/devicetree/bindings/arm/bcm/bcm63138.txt

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+9 −0
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Broadcom BCM63138 DSL System-on-a-Chip device tree bindings

-----------------------------------------------------------



Boards compatible with the BCM63138 DSL System-on-a-Chip should have the

following properties:



Required root node property:



compatible: should be "brcm,bcm63138"

MAINTAINERS

+8 −0
Original line number Diff line number Diff line
@@ -2033,6 +2033,14 @@ F: arch/arm/mach-bcm/bcm_5301x.c 
F:	arch/arm/boot/dts/bcm5301x.dtsi

F:	arch/arm/boot/dts/bcm470*



BROADCOM BCM63XX ARM ARCHITECTURE

M:	Florian Fainelli <f.fainelli@gmail.com>

L:	linux-arm-kernel@lists.infradead.org

T:	git git://git.github.com/brcm/linux.git

S:	Maintained

F:	arch/arm/mach-bcm/bcm63xx.c

F:	arch/arm/include/debug/bcm63xx.S



BROADCOM BCM7XXX ARM ARCHITECTURE

M:	Marc Carino <marc.ceeeee@gmail.com>

M:	Brian Norris <computersforpeace@gmail.com>

arch/arm/Kconfig.debug

+16 −2
Original line number Diff line number Diff line
@@ -122,6 +122,11 @@ choice 
		  mobile SoCs in the Kona family of chips (e.g. bcm28155,

		  bcm11351, etc...)



	config DEBUG_BCM63XX

		bool "Kernel low-level debugging on BCM63XX UART"

		depends on ARCH_BCM_63XX

		select DEBUG_UART_BCM63XX



	config DEBUG_BERLIN_UART

		bool "Marvell Berlin SoC Debug UART"

		depends on ARCH_BERLIN
@@ -1062,6 +1067,7 @@ config DEBUG_LL_INCLUDE 
	default "debug/vf.S" if DEBUG_VF_UART

	default "debug/vt8500.S" if DEBUG_VT8500_UART0

	default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1

	default "debug/bcm63xx.S" if DEBUG_UART_BCM63XX

	default "mach/debug-macro.S"



# Compatibility options for PL01x
@@ -1081,6 +1087,10 @@ config DEBUG_UART_8250 
		ARCH_IOP33X || ARCH_IXP4XX || \

		ARCH_LPC32XX || ARCH_MV78XX0 || ARCH_ORION5X || ARCH_RPC



# Compatibility options for BCM63xx

config DEBUG_UART_BCM63XX

	def_bool ARCH_BCM_63XX



config DEBUG_UART_PHYS

	hex "Physical base address of debug UART"

	default 0x01c20000 if DEBUG_DAVINCI_DMx_UART0
@@ -1149,11 +1159,13 @@ config DEBUG_UART_PHYS 
	default 0xffc02000 if DEBUG_SOCFPGA_UART

	default 0xffd82340 if ARCH_IOP13XX

	default 0xfff36000 if DEBUG_HIGHBANK_UART

	default 0xfffe8600 if DEBUG_UART_BCM63XX

	default 0xfffff700 if ARCH_IOP33X

	depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \

		DEBUG_LL_UART_EFM32 || \

		DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \

		DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART

		DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \

		DEBUG_UART_BCM63XX



config DEBUG_UART_VIRT

	hex "Virtual base address of debug UART"
@@ -1186,6 +1198,7 @@ config DEBUG_UART_VIRT 
	default 0xfa71e000 if DEBUG_QCOM_UARTDM

	default 0xfb009000 if DEBUG_REALVIEW_STD_PORT

	default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT

	default 0xfcfe8600 if DEBUG_UART_BCM63XX

	default 0xfd000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX

	default 0xfd000000 if ARCH_SPEAR13XX

	default 0xfd012000 if ARCH_MV78XX0
@@ -1224,7 +1237,8 @@ config DEBUG_UART_VIRT 
	default DEBUG_UART_PHYS if !MMU

	depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \

		DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \

		DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART

		DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \

		DEBUG_UART_BCM63XX



config DEBUG_UART_8250_SHIFT

	int "Register offset shift for the 8250 debug UART"

arch/arm/boot/dts/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -53,6 +53,7 @@ dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb 
dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb

dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb

dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb

dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb

dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \

	bcm21664-garnet.dtb

dtb-$(CONFIG_ARCH_BERLIN) += \

arch/arm/boot/dts/bcm63138.dtsi

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/*

 * Broadcom BCM63138 DSL SoCs Device Tree

 */



#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/interrupt-controller/irq.h>



#include "skeleton.dtsi"



/ {

	compatible = "brcm,bcm63138";

	model = "Broadcom BCM63138 DSL SoC";

	interrupt-parent = <&gic>;



	aliases {

		uart0 = &serial0;

		uart1 = &serial1;

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			next-level-cache = <&L2>;

			reg = <0>;

		};



		cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			next-level-cache = <&L2>;

			reg = <1>;

		};

	};



	clocks {

		#address-cells = <1>;

		#size-cells = <0>;



		arm_timer_clk: arm_timer_clk {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <500000000>;

		};



		periph_clk: periph_clk {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <50000000>;

			clock-output-names = "periph";

		};

	};



	/* ARM bus */

	axi@80000000 {

		compatible = "simple-bus";

		ranges = <0 0x80000000 0x784000>;

		#address-cells = <1>;

		#size-cells = <1>;



		L2: cache-controller@1d000 {

			compatible = "arm,pl310-cache";

			reg = <0x1d000 0x1000>;

			cache-unified;

			cache-level = <2>;

			cache-sets = <16>;

			cache-size = <0x80000>;

			interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;

		};



		scu: scu@1e000 {

			compatible = "arm,cortex-a9-scu";

			reg = <0x1e000 0x100>;

		};



		gic: interrupt-controller@1e100 {

			compatible = "arm,cortex-a9-gic";

			reg = <0x1f000 0x1000

				0x1e100 0x100>;

			#interrupt-cells = <3>;

			#address-cells = <0>;

			interrupt-controller;

		};



		global_timer: timer@1e200 {

			compatible = "arm,cortex-a9-global-timer";

			reg = <0x1e200 0x20>;

			interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&arm_timer_clk>;

		};



		local_timer: local-timer@1e600 {

			compatible = "arm,cortex-a9-twd-timer";

			reg = <0x1e600 0x20>;

			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&arm_timer_clk>;

		};



		twd_watchdog: watchdog@1e620 {

			compatible = "arm,cortex-a9-twd-wdt";

			reg = <0x1e620 0x20>;

			interupts = <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>;

		};

	};



	/* Legacy UBUS base */

	ubus@fffe8000 {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0xfffe8000 0x8100>;



		serial0: serial@600 {

			compatible = "brcm,bcm6345-uart";

			reg = <0x600 0x1b>;

			interrupts = <GIC_SPI 32 0>;

			clocks = <&periph_clk>;

			clock-names = "periph";

			status = "disabled";

		};



		serial1: serial@620 {

			compatible = "brcm,bcm6345-uart";

			reg = <0x620 0x1b>;

			interrupts = <GIC_SPI 33 0>;

			clocks = <&periph_clk>;

			clock-names = "periph";

			status = "disabled";

		};

	};

};

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