arm64: dts: qcom: sdm845: Add qspi (quad SPI) node (e1ce8539) · Commits · 戴 / test

This adds the Quad SPI controller to the main sdm845 device tree file. Boards will be expected to assign the proper pinctrl depending on how many chip selects they have hooked up and how many data lines. This depends on commit ("clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header") to add the needed defines. It also shouldn't land until the patch ("dt-bindings: spi: Qualcomm Quad SPI(QSPI) documentation") [1] lands. [1] https://lkml.kernel.org/r/20181002214709.162330-1-ryandcase@chromium.org Reviewed-by:

Stephen Boyd <swboyd@chromium.org> Signed-off-by:

Douglas Anderson <dianders@chromium.org> Signed-off-by:

Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:

Andy Gross <andy.gross@linaro.org>

arch/arm64/boot/dts/qcom/sdm845.dtsi

+47 −0

Original line number	Diff line number	Diff line
		@@ -1069,6 +1069,41 @@
		interrupt-controller;
		#interrupt-cells = <2>;

		qspi_clk: qspi-clk {
		pinmux {
		pins = "gpio95";
		function = "qspi_clk";
		};
		};

		qspi_cs0: qspi-cs0 {
		pinmux {
		pins = "gpio90";
		function = "qspi_cs";
		};
		};

		qspi_cs1: qspi-cs1 {
		pinmux {
		pins = "gpio89";
		function = "qspi_cs";
		};
		};

		qspi_data01: qspi-data01 {
		pinmux-data {
		pins = "gpio91", "gpio92";
		function = "qspi_data";
		};
		};

		qspi_data12: qspi-data12 {
		pinmux-data {
		pins = "gpio93", "gpio94";
		function = "qspi_data";
		};
		};

		qup_i2c0_default: qup-i2c0-default {
		pinmux {
		pins = "gpio0", "gpio1";
		@@ -1437,6 +1472,18 @@
		status = "disabled";
		};

		qspi: spi@88df000 {
		compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
		reg = <0x88df000 0x600>;
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
		<&gcc GCC_QSPI_CORE_CLK>;
		clock-names = "iface", "core";
		status = "disabled";
		};

		usb_1_hsphy: phy@88e2000 {
		compatible = "qcom,sdm845-qusb2-phy";
		reg = <0x88e2000 0x400>;

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