ARM: 7924/1: mm: don't bother with reserved ttbr0 when running with LPAE (e1a5848e) · Commits · 戴 / test

With the new ASID allocation algorithm, active ASIDs at the time of a rollover event will be marked as reserved, so active mm_structs can continue to operate with the same ASID as before. This in turn means that we don't need to worry about allocating a new ASID to an mm that is currently active (installed in TTBR0). Since updating the pgd and ASID is atomic on LPAE systems (by virtue of the two being fields in the same hardware register), we can dispose of the reserved TTBR0 and rely on whatever tables we currently have live. Reviewed-by:

Catalin Marinas <catalin.marinas@arm.com> Signed-off-by:

Will Deacon <will.deacon@arm.com> Signed-off-by:

Russell King <rmk+kernel@arm.linux.org.uk>

arch/arm/mm/context.c

+11 −10

Original line number	Original line	Diff line number	Diff line
	@@ -78,20 +78,21 @@ void a15_erratum_get_cpumask(int this_cpu, struct mm_struct *mm,
	#endif		#endif

	#ifdef CONFIG_ARM_LPAE		#ifdef CONFIG_ARM_LPAE
	static void cpu_set_reserved_ttbr0(void)
	{
	/*		/*
	* Set TTBR0 to swapper_pg_dir which contains only global entries. The		* With LPAE, the ASID and page tables are updated atomicly, so there is
	* ASID is set to 0.		* no need for a reserved set of tables (the active ASID tracking prevents
			* any issues across a rollover).
	*/		*/
	cpu_set_ttbr(0, __pa(swapper_pg_dir));		#define cpu_set_reserved_ttbr0()
	isb();
	}
	#else		#else
	static void cpu_set_reserved_ttbr0(void)		static void cpu_set_reserved_ttbr0(void)
	{		{
	u32 ttb;		u32 ttb;
	/* Copy TTBR1 into TTBR0 */		/*
			* Copy TTBR1 into TTBR0.
			* This points at swapper_pg_dir, which contains only global
			* entries so any speculative walks are perfectly safe.
			*/
	asm volatile(		asm volatile(
	" mrc p15, 0, %0, c2, c0, 1 @ read TTBR1\n"		" mrc p15, 0, %0, c2, c0, 1 @ read TTBR1\n"
	" mcr p15, 0, %0, c2, c0, 0 @ set TTBR0\n"		" mcr p15, 0, %0, c2, c0, 0 @ set TTBR0\n"

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