Commit e18f6471 authored by Leonard Crestez's avatar Leonard Crestez Committed by Shawn Guo
Browse files

clk: imx: Mark dram pll on 8mm and 8mn with CLK_GET_RATE_NOCACHE 



DRAM frequency switches are executed in firmware and can change the
configuration of the DRAM PLL outside linux. Mark these CLKs with
CLK_GET_RATE_NOCACHE so we always read back the PLL config registers and
recalculate rates.

In current DRAM frequency tables on 8mm/8mn only the maximum frequency
uses the PLL so it's always configured in the same way. However reading
back the PLL configuration is the correct behavior and allows additional
setpoints in the future.

Signed-off-by: default avatarLeonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: default avatarAbel Vesa <abel.vesa@nxp.com>
Acked-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent d9ea9ca2

drivers/clk/imx/clk-imx8mm.c

+1 −1
Original line number Diff line number Diff line
@@ -328,7 +328,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) 
	clks[IMX8MM_AUDIO_PLL1] = imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll);

	clks[IMX8MM_AUDIO_PLL2] = imx_clk_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll);

	clks[IMX8MM_VIDEO_PLL1] = imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx_1443x_pll);

	clks[IMX8MM_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_pll);

	clks[IMX8MM_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll);

	clks[IMX8MM_GPU_PLL] = imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll);

	clks[IMX8MM_VPU_PLL] = imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx_1416x_pll);

	clks[IMX8MM_ARM_PLL] = imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx_1416x_pll);

drivers/clk/imx/clk-imx8mn.c

+1 −1
Original line number Diff line number Diff line
@@ -325,7 +325,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) 
	clks[IMX8MN_AUDIO_PLL1] = imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll);

	clks[IMX8MN_AUDIO_PLL2] = imx_clk_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll);

	clks[IMX8MN_VIDEO_PLL1] = imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx_1443x_pll);

	clks[IMX8MN_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_pll);

	clks[IMX8MN_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll);

	clks[IMX8MN_GPU_PLL] = imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll);

	clks[IMX8MN_VPU_PLL] = imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx_1416x_pll);

	clks[IMX8MN_ARM_PLL] = imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx_1416x_pll);

drivers/clk/imx/clk-pll14xx.c

+7 −0
Original line number Diff line number Diff line
@@ -67,6 +67,13 @@ struct imx_pll14xx_clk imx_1443x_pll = { 
	.rate_count = ARRAY_SIZE(imx_pll1443x_tbl),

};



struct imx_pll14xx_clk imx_1443x_dram_pll = {

	.type = PLL_1443X,

	.rate_table = imx_pll1443x_tbl,

	.rate_count = ARRAY_SIZE(imx_pll1443x_tbl),

	.flags = CLK_GET_RATE_NOCACHE,

};



struct imx_pll14xx_clk imx_1416x_pll = {

	.type = PLL_1416X,

	.rate_table = imx_pll1416x_tbl,

drivers/clk/imx/clk.h

+1 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ struct imx_pll14xx_clk { 


extern struct imx_pll14xx_clk imx_1416x_pll;

extern struct imx_pll14xx_clk imx_1443x_pll;

extern struct imx_pll14xx_clk imx_1443x_dram_pll;



#define imx_clk_cpu(name, parent_name, div, mux, pll, step) \

	imx_clk_hw_cpu(name, parent_name, div, mux, pll, step)->clk

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