Commit e17b9322 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'mlxsw-Add-support-for-400Gbps-50Gbps-per-lane-link-modes' 



Jiri Pirko says:

====================
mlxsw: Add support for 400Gbps (50Gbps per lane) link modes

Add 400Gbps bits to ethtool and introduce support in mlxsw. These modes
are supported by the Spectrum-2 switch ASIC.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 14f2cf60 5bd29b9b

drivers/net/ethernet/mellanox/mlxsw/reg.h

+1 −0
Original line number Diff line number Diff line
@@ -4111,6 +4111,7 @@ MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 
#define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4		BIT(9)

#define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2		BIT(10)

#define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4		BIT(12)

#define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8				BIT(15)



/* reg_ptys_ext_eth_proto_cap

 * Extended Ethernet port supported speeds and protocols.

drivers/net/ethernet/mellanox/mlxsw/spectrum.c

+42 −10
Original line number Diff line number Diff line
@@ -2912,9 +2912,22 @@ mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4[] = { 
#define MLXSW_SP2_MASK_ETHTOOL_200GAUI_4_200GBASE_CR4_KR4_LEN \

	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4)



static const enum ethtool_link_mode_bit_indices

mlxsw_sp2_mask_ethtool_400gaui_8[] = {

	ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT,

	ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT,

	ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT,

	ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT,

	ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT,

};



#define MLXSW_SP2_MASK_ETHTOOL_400GAUI_8_LEN \

	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_400gaui_8)



#define MLXSW_SP_PORT_MASK_WIDTH_1X	BIT(0)

#define MLXSW_SP_PORT_MASK_WIDTH_2X	BIT(1)

#define MLXSW_SP_PORT_MASK_WIDTH_4X	BIT(2)

#define MLXSW_SP_PORT_MASK_WIDTH_8X	BIT(3)



static u8 mlxsw_sp_port_mask_width_get(u8 width)

{
@@ -2925,6 +2938,8 @@ static u8 mlxsw_sp_port_mask_width_get(u8 width) 
		return MLXSW_SP_PORT_MASK_WIDTH_2X;

	case 4:

		return MLXSW_SP_PORT_MASK_WIDTH_4X;

	case 8:

		return MLXSW_SP_PORT_MASK_WIDTH_8X;

	default:

		WARN_ON_ONCE(1);

		return 0;
@@ -2946,7 +2961,8 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = { 
		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_SGMII_100M_LEN,

		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_1X |

				  MLXSW_SP_PORT_MASK_WIDTH_2X |

				  MLXSW_SP_PORT_MASK_WIDTH_4X,

				  MLXSW_SP_PORT_MASK_WIDTH_4X |

				  MLXSW_SP_PORT_MASK_WIDTH_8X,

		.speed		= SPEED_100,

	},

	{
@@ -2955,7 +2971,8 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = { 
		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_1000BASE_X_SGMII_LEN,

		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_1X |

				  MLXSW_SP_PORT_MASK_WIDTH_2X |

				  MLXSW_SP_PORT_MASK_WIDTH_4X,

				  MLXSW_SP_PORT_MASK_WIDTH_4X |

				  MLXSW_SP_PORT_MASK_WIDTH_8X,

		.speed		= SPEED_1000,

	},

	{
@@ -2964,7 +2981,8 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = { 
		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_2_5GBASE_X_2_5GMII_LEN,

		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_1X |

				  MLXSW_SP_PORT_MASK_WIDTH_2X |

				  MLXSW_SP_PORT_MASK_WIDTH_4X,

				  MLXSW_SP_PORT_MASK_WIDTH_4X |

				  MLXSW_SP_PORT_MASK_WIDTH_8X,

		.speed		= SPEED_2500,

	},

	{
@@ -2973,7 +2991,8 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = { 
		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_5GBASE_R_LEN,

		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_1X |

				  MLXSW_SP_PORT_MASK_WIDTH_2X |

				  MLXSW_SP_PORT_MASK_WIDTH_4X,

				  MLXSW_SP_PORT_MASK_WIDTH_4X |

				  MLXSW_SP_PORT_MASK_WIDTH_8X,

		.speed		= SPEED_5000,

	},

	{
@@ -2982,14 +3001,16 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = { 
		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_XFI_XAUI_1_10G_LEN,

		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_1X |

				  MLXSW_SP_PORT_MASK_WIDTH_2X |

				  MLXSW_SP_PORT_MASK_WIDTH_4X,

				  MLXSW_SP_PORT_MASK_WIDTH_4X |

				  MLXSW_SP_PORT_MASK_WIDTH_8X,

		.speed		= SPEED_10000,

	},

	{

		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G,

		.mask_ethtool	= mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g,

		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_XLAUI_4_XLPPI_4_40G_LEN,

		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_4X,

		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_4X |

				  MLXSW_SP_PORT_MASK_WIDTH_8X,

		.speed		= SPEED_40000,

	},

	{
@@ -2998,7 +3019,8 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = { 
		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_25GAUI_1_25GBASE_CR_KR_LEN,

		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_1X |

				  MLXSW_SP_PORT_MASK_WIDTH_2X |

				  MLXSW_SP_PORT_MASK_WIDTH_4X,

				  MLXSW_SP_PORT_MASK_WIDTH_4X |

				  MLXSW_SP_PORT_MASK_WIDTH_8X,

		.speed		= SPEED_25000,

	},

	{
@@ -3006,7 +3028,8 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = { 
		.mask_ethtool	= mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2,

		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_50GAUI_2_LAUI_2_50GBASE_CR2_KR2_LEN,

		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_2X |

				  MLXSW_SP_PORT_MASK_WIDTH_4X,

				  MLXSW_SP_PORT_MASK_WIDTH_4X |

				  MLXSW_SP_PORT_MASK_WIDTH_8X,

		.speed		= SPEED_50000,

	},

	{
@@ -3020,7 +3043,8 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = { 
		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4,

		.mask_ethtool	= mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4,

		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_CAUI_4_100GBASE_CR4_KR4_LEN,

		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_4X,

		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_4X |

				  MLXSW_SP_PORT_MASK_WIDTH_8X,

		.speed		= SPEED_100000,

	},

	{
@@ -3034,9 +3058,17 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = { 
		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4,

		.mask_ethtool	= mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4,

		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_200GAUI_4_200GBASE_CR4_KR4_LEN,

		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_4X,

		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_4X |

				  MLXSW_SP_PORT_MASK_WIDTH_8X,

		.speed		= SPEED_200000,

	},

	{

		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8,

		.mask_ethtool	= mlxsw_sp2_mask_ethtool_400gaui_8,

		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_400GAUI_8_LEN,

		.mask_width	= MLXSW_SP_PORT_MASK_WIDTH_8X,

		.speed		= SPEED_400000,

	},

};



#define MLXSW_SP2_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp2_port_link_mode)

drivers/net/phy/phy-core.c

+9 −1
Original line number Diff line number Diff line
@@ -8,7 +8,7 @@ 


const char *phy_speed_to_str(int speed)

{

	BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 69,

	BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 74,

		"Enum ethtool_link_mode_bit_indices and phylib are out of sync. "

		"If a speed or mode has been added please update phy_speed_to_str "

		"and the PHY settings array.\n");
@@ -42,6 +42,8 @@ const char *phy_speed_to_str(int speed) 
		return "100Gbps";

	case SPEED_200000:

		return "200Gbps";

	case SPEED_400000:

		return "400Gbps";

	case SPEED_UNKNOWN:

		return "Unknown";

	default:
@@ -70,6 +72,12 @@ EXPORT_SYMBOL_GPL(phy_duplex_to_str); 
			       .bit = ETHTOOL_LINK_MODE_ ## b ## _BIT}



static const struct phy_setting settings[] = {

	/* 400G */

	PHY_SETTING( 400000, FULL, 400000baseCR8_Full		),

	PHY_SETTING( 400000, FULL, 400000baseKR8_Full		),

	PHY_SETTING( 400000, FULL, 400000baseLR8_ER8_FR8_Full	),

	PHY_SETTING( 400000, FULL, 400000baseDR8_Full		),

	PHY_SETTING( 400000, FULL, 400000baseSR8_Full		),

	/* 200G */

	PHY_SETTING( 200000, FULL, 200000baseCR4_Full		),

	PHY_SETTING( 200000, FULL, 200000baseKR4_Full		),

include/uapi/linux/ethtool.h

+6 −0
Original line number Diff line number Diff line
@@ -1507,6 +1507,11 @@ enum ethtool_link_mode_bit_indices { 
	ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT	 = 66,

	ETHTOOL_LINK_MODE_100baseT1_Full_BIT		 = 67,

	ETHTOOL_LINK_MODE_1000baseT1_Full_BIT		 = 68,

	ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT	 = 69,

	ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT	 = 70,

	ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT = 71,

	ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT	 = 72,

	ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT	 = 73,



	/* must be last entry */

	__ETHTOOL_LINK_MODE_MASK_NBITS
@@ -1618,6 +1623,7 @@ enum ethtool_link_mode_bit_indices { 
#define SPEED_56000		56000

#define SPEED_100000		100000

#define SPEED_200000		200000

#define SPEED_400000		400000



#define SPEED_UNKNOWN		-1

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