Merge branch 'for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata

SATA nodes are defined to describe on-chip Serial ATA controllers.

Each SATA controller should have its own node.

It is possible, but not required, to represent each port as a sub-node.

It allows to enable each port independently when dealing with multiple

PHYs.

Required properties:

- compatible        : compatible string, one of:

  - "allwinner,sun4i-a10-ahci"

  - "fsl,imx53-ahci"

  - "fsl,imx6q-ahci"

  - "hisilicon,hisi-ahci"

  - "ibm,476gtr-ahci"

  - "marvell,armada-380-ahci"

  - "snps,dwc-ahci"

  - "snps,exynos5440-ahci"

  - "snps,spear-ahci"

  - "generic-ahci"

- interrupts        : <interrupt mapping for SATA IRQ>

- reg               : <registers mapping>

Please note that when using "generic-ahci" you must also specify a SoC specific

compatible:

	compatible = "manufacturer,soc-model-ahci", "generic-ahci";

Optional properties:

- dma-coherent      : Present if dma operations are coherent

- clocks            : a list of phandle + clock specifier pairs

- target-supply     : regulator for SATA target power

- phys              : reference to the SATA PHY node

- phy-names         : must be "sata-phy"

Required properties when using sub-nodes:

- #address-cells    : number of cells to encode an address

- #size-cells       : number of cells representing the size of an address

Sub-nodes required properties:

- reg               : the port number

- phys              : reference to the SATA PHY node

"fsl,imx53-ahci", "fsl,imx6q-ahci" required properties:

- clocks            : must contain the sata, sata_ref and ahb clocks

- clock-names       : must contain "ahb" for the ahb clock

Examples:

        sata@ffe08000 {

		clocks = <&pll6 0>, <&ahb_gates 25>;

		target-supply = <&reg_ahci_5v>;

	};

With sub-nodes:

	sata@f7e90000 {

		compatible = "marvell,berlin2q-achi", "generic-ahci";

		reg = <0xe90000 0x1000>;

		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&chip CLKID_SATA>;

		#address-cells = <1>;

		#size-cells = <0>;

		sata0: sata-port@0 {

			reg = <0>;

			phys = <&sata_phy 0>;

		};

		sata1: sata-port@1 {

			reg = <1>;

			phys = <&sata_phy 1>;

		};

	};

STMicroelectronics STi SATA controller

This binding describes a SATA device.

Required properties:

 - compatible	   : Must be "st,sti-ahci"

 - reg		   : Physical base addresses and length of register sets

 - interrupts	   : Interrupt associated with the SATA device

 - interrupt-names :   Associated name must be; "hostc"

 - resets	   : The power-down and soft-reset lines of SATA IP

 - reset-names	   :   Associated names must be; "pwr-dwn" and "sw-rst"

 - clocks	   : The phandle for the clock

 - clock-names	   :   Associated name must be; "ahci_clk"

 - phys		   : The phandle for the PHY device

 - phy-names	   :   Associated name must be; "ahci_phy"

Example:

	sata0: sata@fe380000 {

		compatible      = "st,sti-ahci";

		reg             = <0xfe380000 0x1000>;

		interrupts      = <GIC_SPI 157 IRQ_TYPE_NONE>;

		interrupt-names = "hostc";

		phys	        = <&miphy365x_phy MIPHY_PORT_0 MIPHY_TYPE_SATA>;

		phy-names       = "ahci_phy";

		resets	        = <&powerdown STIH416_SATA0_POWERDOWN>,

				  <&softreset STIH416_SATA0_SOFTRESET>;

		reset-names     = "pwr-dwn", "sw-rst";

		clocks	        = <&clk_s_a0_ls CLK_ICN_REG>;

		clock-names     = "ahci_clk";

	};

* Freescale i.MX AHCI SATA Controller

The Freescale i.MX SATA controller mostly conforms to the AHCI interface

with some special extensions at integration level.

Required properties:

- compatible : should be one of the following:

   - "fsl,imx53-ahci" for i.MX53 SATA controller

   - "fsl,imx6q-ahci" for i.MX6Q SATA controller

- interrupts : interrupt mapping for SATA IRQ

- reg : registers mapping

- clocks : list of clock specifiers, must contain an entry for each

  required entry in clock-names

- clock-names : should include "sata", "sata_ref" and "ahb" entries

Optional properties:

- fsl,transmit-level-mV : transmit voltage level, in millivolts.

- fsl,transmit-boost-mdB : transmit boost level, in milli-decibels

- fsl,transmit-atten-16ths : transmit attenuation, in 16ths

- fsl,receive-eq-mdB : receive equalisation, in milli-decibels

  Please refer to the technical documentation or the driver source code

  for the list of legal values for these options.

- fsl,no-spread-spectrum : disable spread-spectrum clocking on the SATA

  link.

Examples:

sata@02200000 {

	compatible = "fsl,imx6q-ahci";

	reg = <0x02200000 0x4000>;

	interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&clks IMX6QDL_CLK_SATA>,

		 <&clks IMX6QDL_CLK_SATA_REF_100M>,

		 <&clks IMX6QDL_CLK_AHB>;

	clock-names = "sata", "sata_ref", "ahb";

};

Tegra124 SoC SATA AHCI controller

Required properties :

- compatible : "nvidia,tegra124-ahci".

- reg : Should contain 2 entries:

  - AHCI register set (SATA BAR5)

  - SATA register set

- interrupts : Defines the interrupt used by SATA

- clocks : Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

- clock-names : Must include the following entries:

  - sata

  - sata-oob

  - cml1

  - pll_e

- resets : Must contain an entry for each entry in reset-names.

  See ../reset/reset.txt for details.

- reset-names : Must include the following entries:

  - sata

  - sata-oob

  - sata-cold

- phys : Must contain an entry for each entry in phy-names.

  See ../phy/phy-bindings.txt for details.

- phy-names : Must include the following entries:

  - sata-phy : XUSB PADCTL SATA PHY

- hvdd-supply : Defines the SATA HVDD regulator

- vddio-supply : Defines the SATA VDDIO regulator

- avdd-supply : Defines the SATA AVDD regulator

- target-5v-supply : Defines the SATA 5V power regulator

- target-12v-supply : Defines the SATA 12V power regulator

	  If unsure, say N.

config AHCI_TEGRA

	tristate "NVIDIA Tegra124 AHCI SATA support"

	depends on ARCH_TEGRA

	help

	  This option enables support for the NVIDIA Tegra124 SoC's

	  onboard AHCI SATA.

	  If unsure, say N.

config AHCI_XGENE

	tristate "APM X-Gene 6.0Gbps AHCI SATA host controller support"

	depends on PHY_XGENE