Commit e173f891 authored Nov 09, 2016 by Ulf Hansson

mmc: core: Update CMD13 polling policy when switch to HS DDR mode

According to the JEDEC specification, during bus timing change operations
for mmc, sending a CMD13 could trigger CRC errors.

As switching to HS DDR mode indeed causes a bus timing change, polling with
CMD13 to detect card busy, may thus potentially trigger CRC errors.
Currently these errors are treated as the switch to HS DDR mode failed.

To improve this behaviour, let's instead tell __mmc_switch() to retry when
it encounters CRC errors during polling.

Moreover, when switching to HS DDR mode, let's make sure the CMD13 polling
is done by having the mmc host and the mmc card, being configured to
operate at the same selected bus speed timing. Fix this by providing
MMC_TIMING_MMC_DDR52 as the timing parameter to __mmc_switch().

Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>

parent 53e60650

drivers/mmc/core/mmc.c

+6 −7

Original line number	Diff line number	Diff line
		@@ -1040,10 +1040,12 @@ static int mmc_select_hs_ddr(struct mmc_card *card)
		ext_csd_bits = (bus_width == MMC_BUS_WIDTH_8) ?
		EXT_CSD_DDR_BUS_WIDTH_8 : EXT_CSD_DDR_BUS_WIDTH_4;

		err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
		err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
		EXT_CSD_BUS_WIDTH,
		ext_csd_bits,
		card->ext_csd.generic_cmd6_time);
		card->ext_csd.generic_cmd6_time,
		MMC_TIMING_MMC_DDR52,
		true, true, true);
		if (err) {
		pr_err("%s: switch to bus width %d ddr failed\n",
		mmc_hostname(host), 1 << bus_width);
		@@ -1086,9 +1088,6 @@ static int mmc_select_hs_ddr(struct mmc_card *card)
		if (err)
		err = __mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_330);

		if (!err)
		mmc_set_timing(host, MMC_TIMING_MMC_DDR52);

		return err;
		}

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