Commit e16393bb authored by Luis R. Rodriguez's avatar Luis R. Rodriguez Committed by John W. Linville
Browse files

ath9k_hw: order phy.c code and integrate spur mitigation 



This reorders phy.c routines in the order in the order in which they are used
and also moves the spur mitigation helpers for each type of chip into phy.c
as they are RF related.

This patch has no functional changes.

Signed-off-by: default avatarLuis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent e68a060b

drivers/net/wireless/ath/ath9k/hw.c

+0 −453
Original line number Diff line number Diff line
@@ -30,8 +30,6 @@ static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan); 
static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,

			      struct ar5416_eeprom_def *pEepData,

			      u32 reg, u32 value);

static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);

static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);



MODULE_AUTHOR("Atheros Communications");

MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
@@ -1930,457 +1928,6 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah, 
	return true;

}



static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)

{

	int bb_spur = AR_NO_SPUR;

	int freq;

	int bin, cur_bin;

	int bb_spur_off, spur_subchannel_sd;

	int spur_freq_sd;

	int spur_delta_phase;

	int denominator;

	int upper, lower, cur_vit_mask;

	int tmp, newVal;

	int i;

	int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,

			  AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60

	};

	int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,

			 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60

	};

	int inc[4] = { 0, 100, 0, 0 };

	struct chan_centers centers;



	int8_t mask_m[123];

	int8_t mask_p[123];

	int8_t mask_amt;

	int tmp_mask;

	int cur_bb_spur;

	bool is2GHz = IS_CHAN_2GHZ(chan);



	memset(&mask_m, 0, sizeof(int8_t) * 123);

	memset(&mask_p, 0, sizeof(int8_t) * 123);



	ath9k_hw_get_channel_centers(ah, chan, &centers);

	freq = centers.synth_center;



	ah->config.spurmode = SPUR_ENABLE_EEPROM;

	for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {

		cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);



		if (is2GHz)

			cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;

		else

			cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;



		if (AR_NO_SPUR == cur_bb_spur)

			break;

		cur_bb_spur = cur_bb_spur - freq;



		if (IS_CHAN_HT40(chan)) {

			if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&

			    (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {

				bb_spur = cur_bb_spur;

				break;

			}

		} else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&

			   (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {

			bb_spur = cur_bb_spur;

			break;

		}

	}



	if (AR_NO_SPUR == bb_spur) {

		REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,

			    AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);

		return;

	} else {

		REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,

			    AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);

	}



	bin = bb_spur * 320;



	tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));



	newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |

			AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |

			AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |

			AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);

	REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);



	newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |

		  AR_PHY_SPUR_REG_ENABLE_MASK_PPM |

		  AR_PHY_SPUR_REG_MASK_RATE_SELECT |

		  AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |

		  SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));

	REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);



	if (IS_CHAN_HT40(chan)) {

		if (bb_spur < 0) {

			spur_subchannel_sd = 1;

			bb_spur_off = bb_spur + 10;

		} else {

			spur_subchannel_sd = 0;

			bb_spur_off = bb_spur - 10;

		}

	} else {

		spur_subchannel_sd = 0;

		bb_spur_off = bb_spur;

	}



	if (IS_CHAN_HT40(chan))

		spur_delta_phase =

			((bb_spur * 262144) /

			 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;

	else

		spur_delta_phase =

			((bb_spur * 524288) /

			 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;



	denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;

	spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;



	newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |

		  SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |

		  SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));

	REG_WRITE(ah, AR_PHY_TIMING11, newVal);



	newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;

	REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);



	cur_bin = -6000;

	upper = bin + 100;

	lower = bin - 100;



	for (i = 0; i < 4; i++) {

		int pilot_mask = 0;

		int chan_mask = 0;

		int bp = 0;

		for (bp = 0; bp < 30; bp++) {

			if ((cur_bin > lower) && (cur_bin < upper)) {

				pilot_mask = pilot_mask | 0x1 << bp;

				chan_mask = chan_mask | 0x1 << bp;

			}

			cur_bin += 100;

		}

		cur_bin += inc[i];

		REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);

		REG_WRITE(ah, chan_mask_reg[i], chan_mask);

	}



	cur_vit_mask = 6100;

	upper = bin + 120;

	lower = bin - 120;



	for (i = 0; i < 123; i++) {

		if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {



			/* workaround for gcc bug #37014 */

			volatile int tmp_v = abs(cur_vit_mask - bin);



			if (tmp_v < 75)

				mask_amt = 1;

			else

				mask_amt = 0;

			if (cur_vit_mask < 0)

				mask_m[abs(cur_vit_mask / 100)] = mask_amt;

			else

				mask_p[cur_vit_mask / 100] = mask_amt;

		}

		cur_vit_mask -= 100;

	}



	tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)

		| (mask_m[48] << 26) | (mask_m[49] << 24)

		| (mask_m[50] << 22) | (mask_m[51] << 20)

		| (mask_m[52] << 18) | (mask_m[53] << 16)

		| (mask_m[54] << 14) | (mask_m[55] << 12)

		| (mask_m[56] << 10) | (mask_m[57] << 8)

		| (mask_m[58] << 6) | (mask_m[59] << 4)

		| (mask_m[60] << 2) | (mask_m[61] << 0);

	REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);

	REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);



	tmp_mask = (mask_m[31] << 28)

		| (mask_m[32] << 26) | (mask_m[33] << 24)

		| (mask_m[34] << 22) | (mask_m[35] << 20)

		| (mask_m[36] << 18) | (mask_m[37] << 16)

		| (mask_m[48] << 14) | (mask_m[39] << 12)

		| (mask_m[40] << 10) | (mask_m[41] << 8)

		| (mask_m[42] << 6) | (mask_m[43] << 4)

		| (mask_m[44] << 2) | (mask_m[45] << 0);

	REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);

	REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);



	tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)

		| (mask_m[18] << 26) | (mask_m[18] << 24)

		| (mask_m[20] << 22) | (mask_m[20] << 20)

		| (mask_m[22] << 18) | (mask_m[22] << 16)

		| (mask_m[24] << 14) | (mask_m[24] << 12)

		| (mask_m[25] << 10) | (mask_m[26] << 8)

		| (mask_m[27] << 6) | (mask_m[28] << 4)

		| (mask_m[29] << 2) | (mask_m[30] << 0);

	REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);

	REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);



	tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)

		| (mask_m[2] << 26) | (mask_m[3] << 24)

		| (mask_m[4] << 22) | (mask_m[5] << 20)

		| (mask_m[6] << 18) | (mask_m[7] << 16)

		| (mask_m[8] << 14) | (mask_m[9] << 12)

		| (mask_m[10] << 10) | (mask_m[11] << 8)

		| (mask_m[12] << 6) | (mask_m[13] << 4)

		| (mask_m[14] << 2) | (mask_m[15] << 0);

	REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);

	REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);



	tmp_mask = (mask_p[15] << 28)

		| (mask_p[14] << 26) | (mask_p[13] << 24)

		| (mask_p[12] << 22) | (mask_p[11] << 20)

		| (mask_p[10] << 18) | (mask_p[9] << 16)

		| (mask_p[8] << 14) | (mask_p[7] << 12)

		| (mask_p[6] << 10) | (mask_p[5] << 8)

		| (mask_p[4] << 6) | (mask_p[3] << 4)

		| (mask_p[2] << 2) | (mask_p[1] << 0);

	REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);

	REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);



	tmp_mask = (mask_p[30] << 28)

		| (mask_p[29] << 26) | (mask_p[28] << 24)

		| (mask_p[27] << 22) | (mask_p[26] << 20)

		| (mask_p[25] << 18) | (mask_p[24] << 16)

		| (mask_p[23] << 14) | (mask_p[22] << 12)

		| (mask_p[21] << 10) | (mask_p[20] << 8)

		| (mask_p[19] << 6) | (mask_p[18] << 4)

		| (mask_p[17] << 2) | (mask_p[16] << 0);

	REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);

	REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);



	tmp_mask = (mask_p[45] << 28)

		| (mask_p[44] << 26) | (mask_p[43] << 24)

		| (mask_p[42] << 22) | (mask_p[41] << 20)

		| (mask_p[40] << 18) | (mask_p[39] << 16)

		| (mask_p[38] << 14) | (mask_p[37] << 12)

		| (mask_p[36] << 10) | (mask_p[35] << 8)

		| (mask_p[34] << 6) | (mask_p[33] << 4)

		| (mask_p[32] << 2) | (mask_p[31] << 0);

	REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);

	REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);



	tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)

		| (mask_p[59] << 26) | (mask_p[58] << 24)

		| (mask_p[57] << 22) | (mask_p[56] << 20)

		| (mask_p[55] << 18) | (mask_p[54] << 16)

		| (mask_p[53] << 14) | (mask_p[52] << 12)

		| (mask_p[51] << 10) | (mask_p[50] << 8)

		| (mask_p[49] << 6) | (mask_p[48] << 4)

		| (mask_p[47] << 2) | (mask_p[46] << 0);

	REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);

	REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);

}



static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)

{

	int bb_spur = AR_NO_SPUR;

	int bin, cur_bin;

	int spur_freq_sd;

	int spur_delta_phase;

	int denominator;

	int upper, lower, cur_vit_mask;

	int tmp, new;

	int i;

	int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,

			  AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60

	};

	int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,

			 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60

	};

	int inc[4] = { 0, 100, 0, 0 };



	int8_t mask_m[123];

	int8_t mask_p[123];

	int8_t mask_amt;

	int tmp_mask;

	int cur_bb_spur;

	bool is2GHz = IS_CHAN_2GHZ(chan);



	memset(&mask_m, 0, sizeof(int8_t) * 123);

	memset(&mask_p, 0, sizeof(int8_t) * 123);



	for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {

		cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);

		if (AR_NO_SPUR == cur_bb_spur)

			break;

		cur_bb_spur = cur_bb_spur - (chan->channel * 10);

		if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {

			bb_spur = cur_bb_spur;

			break;

		}

	}



	if (AR_NO_SPUR == bb_spur)

		return;



	bin = bb_spur * 32;



	tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));

	new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |

		     AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |

		     AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |

		     AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);



	REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);



	new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |

	       AR_PHY_SPUR_REG_ENABLE_MASK_PPM |

	       AR_PHY_SPUR_REG_MASK_RATE_SELECT |

	       AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |

	       SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));

	REG_WRITE(ah, AR_PHY_SPUR_REG, new);



	spur_delta_phase = ((bb_spur * 524288) / 100) &

		AR_PHY_TIMING11_SPUR_DELTA_PHASE;



	denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;

	spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;



	new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |

	       SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |

	       SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));

	REG_WRITE(ah, AR_PHY_TIMING11, new);



	cur_bin = -6000;

	upper = bin + 100;

	lower = bin - 100;



	for (i = 0; i < 4; i++) {

		int pilot_mask = 0;

		int chan_mask = 0;

		int bp = 0;

		for (bp = 0; bp < 30; bp++) {

			if ((cur_bin > lower) && (cur_bin < upper)) {

				pilot_mask = pilot_mask | 0x1 << bp;

				chan_mask = chan_mask | 0x1 << bp;

			}

			cur_bin += 100;

		}

		cur_bin += inc[i];

		REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);

		REG_WRITE(ah, chan_mask_reg[i], chan_mask);

	}



	cur_vit_mask = 6100;

	upper = bin + 120;

	lower = bin - 120;



	for (i = 0; i < 123; i++) {

		if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {



			/* workaround for gcc bug #37014 */

			volatile int tmp_v = abs(cur_vit_mask - bin);



			if (tmp_v < 75)

				mask_amt = 1;

			else

				mask_amt = 0;

			if (cur_vit_mask < 0)

				mask_m[abs(cur_vit_mask / 100)] = mask_amt;

			else

				mask_p[cur_vit_mask / 100] = mask_amt;

		}

		cur_vit_mask -= 100;

	}



	tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)

		| (mask_m[48] << 26) | (mask_m[49] << 24)

		| (mask_m[50] << 22) | (mask_m[51] << 20)

		| (mask_m[52] << 18) | (mask_m[53] << 16)

		| (mask_m[54] << 14) | (mask_m[55] << 12)

		| (mask_m[56] << 10) | (mask_m[57] << 8)

		| (mask_m[58] << 6) | (mask_m[59] << 4)

		| (mask_m[60] << 2) | (mask_m[61] << 0);

	REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);

	REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);



	tmp_mask = (mask_m[31] << 28)

		| (mask_m[32] << 26) | (mask_m[33] << 24)

		| (mask_m[34] << 22) | (mask_m[35] << 20)

		| (mask_m[36] << 18) | (mask_m[37] << 16)

		| (mask_m[48] << 14) | (mask_m[39] << 12)

		| (mask_m[40] << 10) | (mask_m[41] << 8)

		| (mask_m[42] << 6) | (mask_m[43] << 4)

		| (mask_m[44] << 2) | (mask_m[45] << 0);

	REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);

	REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);



	tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)

		| (mask_m[18] << 26) | (mask_m[18] << 24)

		| (mask_m[20] << 22) | (mask_m[20] << 20)

		| (mask_m[22] << 18) | (mask_m[22] << 16)

		| (mask_m[24] << 14) | (mask_m[24] << 12)

		| (mask_m[25] << 10) | (mask_m[26] << 8)

		| (mask_m[27] << 6) | (mask_m[28] << 4)

		| (mask_m[29] << 2) | (mask_m[30] << 0);

	REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);

	REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);



	tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)

		| (mask_m[2] << 26) | (mask_m[3] << 24)

		| (mask_m[4] << 22) | (mask_m[5] << 20)

		| (mask_m[6] << 18) | (mask_m[7] << 16)

		| (mask_m[8] << 14) | (mask_m[9] << 12)

		| (mask_m[10] << 10) | (mask_m[11] << 8)

		| (mask_m[12] << 6) | (mask_m[13] << 4)

		| (mask_m[14] << 2) | (mask_m[15] << 0);

	REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);

	REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);



	tmp_mask = (mask_p[15] << 28)

		| (mask_p[14] << 26) | (mask_p[13] << 24)

		| (mask_p[12] << 22) | (mask_p[11] << 20)

		| (mask_p[10] << 18) | (mask_p[9] << 16)

		| (mask_p[8] << 14) | (mask_p[7] << 12)

		| (mask_p[6] << 10) | (mask_p[5] << 8)

		| (mask_p[4] << 6) | (mask_p[3] << 4)

		| (mask_p[2] << 2) | (mask_p[1] << 0);

	REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);

	REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);



	tmp_mask = (mask_p[30] << 28)

		| (mask_p[29] << 26) | (mask_p[28] << 24)

		| (mask_p[27] << 22) | (mask_p[26] << 20)

		| (mask_p[25] << 18) | (mask_p[24] << 16)

		| (mask_p[23] << 14) | (mask_p[22] << 12)

		| (mask_p[21] << 10) | (mask_p[20] << 8)

		| (mask_p[19] << 6) | (mask_p[18] << 4)

		| (mask_p[17] << 2) | (mask_p[16] << 0);

	REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);

	REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);



	tmp_mask = (mask_p[45] << 28)

		| (mask_p[44] << 26) | (mask_p[43] << 24)

		| (mask_p[42] << 22) | (mask_p[41] << 20)

		| (mask_p[40] << 18) | (mask_p[39] << 16)

		| (mask_p[38] << 14) | (mask_p[37] << 12)

		| (mask_p[36] << 10) | (mask_p[35] << 8)

		| (mask_p[34] << 6) | (mask_p[33] << 4)

		| (mask_p[32] << 2) | (mask_p[31] << 0);

	REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);

	REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);



	tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)

		| (mask_p[59] << 26) | (mask_p[58] << 24)

		| (mask_p[57] << 22) | (mask_p[56] << 20)

		| (mask_p[55] << 18) | (mask_p[54] << 16)

		| (mask_p[53] << 14) | (mask_p[52] << 12)

		| (mask_p[51] << 10) | (mask_p[50] << 8)

		| (mask_p[49] << 6) | (mask_p[48] << 4)

		| (mask_p[47] << 2) | (mask_p[46] << 0);

	REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);

	REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);

}



static void ath9k_enable_rfkill(struct ath_hw *ah)

{

	REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,

drivers/net/wireless/ath/ath9k/phy.c

+623 −156

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/wireless/ath/ath9k/phy.h

+14 −5
Original line number Diff line number Diff line
@@ -17,19 +17,28 @@ 
#ifndef PHY_H

#define PHY_H



int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);

int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);

/* Common between single chip and non single-chip solutions */

void ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex,

			 u32 freqIndex, int regWrites);



/* Single chip radio settings */

int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);

void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);



/* Routines below are for non single-chip solutions */

int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);

void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);



int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah);

void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah);



bool ath9k_hw_set_rf_regs(struct ath_hw *ah,

			  struct ath9k_channel *chan,

			  u16 modesIndex);



void ath9k_hw_decrease_chain_power(struct ath_hw *ah,

				   struct ath9k_channel *chan);



void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah);

int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah);



#define AR_PHY_BASE     0x9800

#define AR_PHY(_n)      (AR_PHY_BASE + ((_n)<<2))

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