Commit e0f7a8d5 authored by Catalin Marinas's avatar Catalin Marinas
Browse files

Merge branch 'for-next/uaccess' into for-next/core 

* for-next/uaccess:
  : uaccess routines clean-up and set_fs() removal
  arm64: mark __system_matches_cap as __maybe_unused
  arm64: uaccess: remove vestigal UAO support
  arm64: uaccess: remove redundant PAN toggling
  arm64: uaccess: remove addr_limit_user_check()
  arm64: uaccess: remove set_fs()
  arm64: uaccess cleanup macro naming
  arm64: uaccess: split user/kernel routines
  arm64: uaccess: refactor __{get,put}_user
  arm64: uaccess: simplify __copy_user_flushcache()
  arm64: uaccess: rename privileged uaccess routines
  arm64: sdei: explicitly simulate PAN/UAO entry
  arm64: sdei: move uaccess logic to arch/arm64/
  arm64: head.S: always initialize PSTATE
  arm64: head.S: cleanup SCTLR_ELx initialization
  arm64: head.S: rename el2_setup -> init_kernel_el
  arm64: add C wrappers for SET_PSTATE_*()
  arm64: ensure ERET from kthread is illegal
parents 3c09ec59 701f4906

arch/arm64/Kconfig

+0 −22
Original line number Diff line number Diff line
@@ -195,7 +195,6 @@ config ARM64 
	select PCI_SYSCALL if PCI

	select POWER_RESET

	select POWER_SUPPLY

	select SET_FS

	select SPARSE_IRQ

	select SWIOTLB

	select SYSCTL_EXCEPTION_TRACE
@@ -1428,27 +1427,6 @@ endmenu 


menu "ARMv8.2 architectural features"



config ARM64_UAO

	bool "Enable support for User Access Override (UAO)"

	default y

	help

	  User Access Override (UAO; part of the ARMv8.2 Extensions)

	  causes the 'unprivileged' variant of the load/store instructions to

	  be overridden to be privileged.



	  This option changes get_user() and friends to use the 'unprivileged'

	  variant of the load/store instructions. This ensures that user-space

	  really did have access to the supplied memory. When addr_limit is

	  set to kernel memory the UAO bit will be set, allowing privileged

	  access to kernel memory.



	  Choosing this option will cause copy_to_user() et al to use user-space

	  memory permissions.



	  The feature is detected at runtime, the kernel will use the

	  regular load/store instructions if the cpu does not implement the

	  feature.



config ARM64_PMEM

	bool "Enable support for persistent memory"

	select ARCH_HAS_PMEM_API

arch/arm64/include/asm/asm-uaccess.h

+12 −42
Original line number Diff line number Diff line
@@ -59,62 +59,32 @@ alternative_else_nop_endif 
#endif



/*

 * Generate the assembly for UAO alternatives with exception table entries.

 * Generate the assembly for LDTR/STTR with exception table entries.

 * This is complicated as there is no post-increment or pair versions of the

 * unprivileged instructions, and USER() only works for single instructions.

 */

#ifdef CONFIG_ARM64_UAO

	.macro uao_ldp l, reg1, reg2, addr, post_inc

		alternative_if_not ARM64_HAS_UAO

8888:			ldp	\reg1, \reg2, [\addr], \post_inc;

8889:			nop;

			nop;

		alternative_else

			ldtr	\reg1, [\addr];

			ldtr	\reg2, [\addr, #8];

	.macro user_ldp l, reg1, reg2, addr, post_inc

8888:		ldtr	\reg1, [\addr];

8889:		ldtr	\reg2, [\addr, #8];

		add	\addr, \addr, \post_inc;

		alternative_endif



		_asm_extable	8888b,\l;

		_asm_extable	8889b,\l;

	.endm



	.macro uao_stp l, reg1, reg2, addr, post_inc

		alternative_if_not ARM64_HAS_UAO

8888:			stp	\reg1, \reg2, [\addr], \post_inc;

8889:			nop;

			nop;

		alternative_else

			sttr	\reg1, [\addr];

			sttr	\reg2, [\addr, #8];

	.macro user_stp l, reg1, reg2, addr, post_inc

8888:		sttr	\reg1, [\addr];

8889:		sttr	\reg2, [\addr, #8];

		add	\addr, \addr, \post_inc;

		alternative_endif



		_asm_extable	8888b,\l;

		_asm_extable	8889b,\l;

	.endm



	.macro uao_user_alternative l, inst, alt_inst, reg, addr, post_inc

		alternative_if_not ARM64_HAS_UAO

8888:			\inst	\reg, [\addr], \post_inc;

			nop;

		alternative_else

			\alt_inst	\reg, [\addr];

	.macro user_ldst l, inst, reg, addr, post_inc

8888:		\inst		\reg, [\addr];

		add		\addr, \addr, \post_inc;

		alternative_endif



		_asm_extable	8888b,\l;

	.endm

#else

	.macro uao_ldp l, reg1, reg2, addr, post_inc

		USER(\l, ldp \reg1, \reg2, [\addr], \post_inc)

	.endm

	.macro uao_stp l, reg1, reg2, addr, post_inc

		USER(\l, stp \reg1, \reg2, [\addr], \post_inc)

	.endm

	.macro uao_user_alternative l, inst, alt_inst, reg, addr, post_inc

		USER(\l, \inst \reg, [\addr], \post_inc)

	.endm

#endif



#endif

arch/arm64/include/asm/cpucaps.h

+0 −2
Original line number Diff line number Diff line
@@ -16,8 +16,6 @@ 
#define ARM64_WORKAROUND_CAVIUM_23154		6

#define ARM64_WORKAROUND_834220			7

#define ARM64_HAS_NO_HW_PREFETCH		8

#define ARM64_HAS_UAO				9

#define ARM64_ALT_PAN_NOT_UAO			10

#define ARM64_HAS_VIRT_HOST_EXTN		11

#define ARM64_WORKAROUND_CAVIUM_27456		12

#define ARM64_HAS_32BIT_EL0			13

arch/arm64/include/asm/cpufeature.h

+14 −1
Original line number Diff line number Diff line
@@ -667,10 +667,16 @@ static __always_inline bool system_supports_fpsimd(void) 
	return !cpus_have_const_cap(ARM64_HAS_NO_FPSIMD);

}



static inline bool system_uses_hw_pan(void)

{

	return IS_ENABLED(CONFIG_ARM64_PAN) &&

		cpus_have_const_cap(ARM64_HAS_PAN);

}



static inline bool system_uses_ttbr0_pan(void)

{

	return IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN) &&

		!cpus_have_const_cap(ARM64_HAS_PAN);

		!system_uses_hw_pan();

}



static __always_inline bool system_supports_sve(void)
@@ -762,6 +768,13 @@ static inline bool cpu_has_hw_af(void) 
						ID_AA64MMFR1_HADBS_SHIFT);

}



static inline bool cpu_has_pan(void)

{

	u64 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);

	return cpuid_feature_extract_unsigned_field(mmfr1,

						    ID_AA64MMFR1_PAN_SHIFT);

}



#ifdef CONFIG_ARM64_AMU_EXTN

/* Check whether the cpu supports the Activity Monitors Unit (AMU) */

extern bool cpu_has_amu_feat(int cpu);

arch/arm64/include/asm/exec.h

+0 −1
Original line number Diff line number Diff line
@@ -10,6 +10,5 @@ 
#include <linux/sched.h>



extern unsigned long arch_align_stack(unsigned long sp);

void uao_thread_switch(struct task_struct *next);



#endif	/* __ASM_EXEC_H */

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